Architecture and Design Methodology for Autonomic Systems-on-Chip - - PowerPoint PPT Presentation

Architecture and Design Methodology for Autonomic Systems-on-Chip (ASoC)

Universität Tübingen Technische Universität München FZI - Forschungszentrum Informatik

• A. Bernauer, A. Bouajila, J. Zeppenfeld, W. Stechele, O. Bringmann,
• A. Herkersdorf, W. Rosenstiel

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Project Reminder

Application

Requirements & Characteristics

Architecture

Characteristics

FE/AE

Parameter Selection

FE/AE

Model

Evaluation

Architecture Optimization

Functional

SoC elements

Autonomic

SoC elements

Performance Reliability Power FUNCTIONAL Layer AUTONOMIC Layer Autonomic Element Functional Element

October 7, 2010 ASoC - Architecture and Design Methodology for SoC

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Phase 3 Work Packages

October 7, 2010 ASoC - Architecture and Design Methodology for SoC

Demonstrator Combining XCS and LCT Estimating minimum population size Distributed XCS Run-time reliability

• ptimization

Distributed XCS

• Cooperating XCS instances:

benefits for self-adaptation?

• Simplified Cell processor,

different cooling properties for each core

• Varying ambient temperature and activity
• Goal: maximum performance, but no timing errors
• Configurations

– Topology: uni-, bidirectional, complete graph – Emigration strategy: random, numerosity, prediction error – Deletion strategy: by fitness, prediction error – Don’t care probability: 0.1, 0.3, 0.6, 0.9

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Isolated XCS

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P#=0.3 P#=0.9 SXU2

Distributed XCS

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P#=0.3 P#=0.9 Topology: complete Emigration: selecting by fitness Deletion: selecting by prediction error SXU2

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Phase 3 Work Packages

October 7, 2010 ASoC - Architecture and Design Methodology for SoC

Combining XCS and LCT

Combining XCS and LCT

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Design-time rule set Action Fitness update Rule set update Initial rule set Run-time rule set Action Fitness update Rule set update

Rule-set translation HW SW Design-time learning (XCS) Software Run-time learning (LCT) Hardware

Goals:

• retain capability to self-adapt to unforeseen events
• low hardware overhead

[BICC10]

Configurations and benchmarks

• Rule translation

– all-XCS: translate all XCS rules to LCT rules – top-XCS: translate only top XCS rules

• Action selection

– roulette-wheel: randomly, reward-weighted – winner-takes-all: highest reward

• Benchmarks

– Multiplexer – Task allocation – SoC component parameterization

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0 1 2 5 4 3 6 7 8

task allocation

• n 9 cores

[BICC10]

Task allocation benchmark

October 7, 2010 ASoC - Architecture and Design Methodology for SoC 11 L: Number of cores i: Number of tasks

[BICC10]

Task allocation benchmark

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L: Number of cores i: Number of tasks

Single core failure in LCT Double core failure in LCT  Self-adaptation at chip level with all-XCS rule translation and winner-takes-all action selection strategy [BICC10]

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Phase 3 Work Packages

October 7, 2010 ASoC - Architecture and Design Methodology for SoC

Estimating minimum population size

Estimating minimum population size N

• State of the art: Calculate N for “regular” problems

– “Regular” problem: constant number of relevant bits per problem instance – Example: Multiplexer problem 01 1101  0 (3 relevant bits)

• Our extension: Calculate N for “complex” problems

– “Complex” problem: variable number of relevant bits per problem instance – Example: 2-out-of-4 task allocation problem allocation possible 1100  2 (2 relevant bits) allocation impossible 1110  0 (3 relevant bits)

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[IJCNN10]

Estimating minimum population size N

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[IJCNN10]

Experimental results: → Estimated N is an upper bound; Performance penalty if using smaller N

(e.g., when using only 0.75N, only 70% of the problem instances have correctness rate >90%)

Trading classifiers for accuracy

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• Idea: subsume classifiers

during rule translation, after learning

• Higher correctness rate

than when subsuming during learning (SASO [9])

• Comparable population

size with SASO [9]

[IJCNN10]

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Phase 3 Work Packages

October 7, 2010 ASoC - Architecture and Design Methodology for SoC

Run-time reliability

• ptimization

Run-time reliability optimization

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Modular redundancy Series

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Phase 3 Work Packages

October 7, 2010 ASoC - Architecture and Design Methodology for SoC

Demonstrator

Demonstrator – Hardware

• Monitors

– Frequency (3 bit) – Utilization (3 bit) – Workload difference (2 bit)

• Actuators

– Frequency (4 bit) – Task migration (1 bit)

• Evaluator

– Learning classifier system adapted for efficient HW implementation

• Communicator

– Sharing of global information – Migration of tasks

MEM UART MAC Core1 Core2 Core3 Bus Condition Action Fitness 1 X X X 1 X 1 X X : 1001 : 1010 : 1100 11 3 15

. . . . . . . . .

Learning Classifier Table Fitness Update

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MEM UART MAC Bus Condition Action Fitness 1 X X X 1 X 1 X X : 1001 : 1010 : 1100 11 3 15

. . . . . . . . .

Learning Classifier Table Fitness Update

Demonstrator – Tasks

• Test tasks 1-N

– Adjustable, synthetic workloads – After completion, pass data to next task

• User interface

– Allow for user interaction

• Data generation

– Replaces packet reception for standalone demonstration – Generates new data packet every 100µs T1 T2 T3 T4 T5

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Core1 Core2 Core3

• UART

– Pass buffered output data to the UART

Demonstration

Hardware Overheads

Flip-Flops LUTs BRAMs Mult. Overhead Leon3 1749 8936 28 1 – Leon3 AE 2122 10213 29 2 14.3% LCT 66 116 1 1 1.4% Act Task. 57 299 3.5% Act Freq. 7 19 0.2% Mon Util. 35 74 0.8% Mon Load 20 40 0.5% AE IF 173 399 4.5%

Synthesis results for Xilinx Virtex 4 VLX100 October 7, 2010 ASoC - Architecture and Design Methodology for SoC 23

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Phase 3 Progress

October 7, 2010 ASoC - Architecture and Design Methodology for SoC

• 3rd LCS-Workshop, Tübingen, July 1-2, 2010

Future work

• Continue work on Autonomic Layer reliability
• Complete dependability assessment
• Reduce simulation time due to temperature estimation
• Extend theoretical analysis to run-time system
• Complete work on demonstrator

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Summary

• Distributed XCS, solves previously difficult to solve problems
• Combining Software XCS with Hardware LCT

for Lightweight On-Chip Learning

• Estimating minimum population size N
• Trading classifiers for accuracy
• Demonstrator runs 3 Leon3 cores, distributes tasks and

adjusts frequency autonomously

October 7, 2010 ASoC - Architecture and Design Methodology for SoC

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Recent Publications

• [ARCS10] J. Zeppenfeld, A. Herkersdorf. Autonomic Workload Management for Multi-Core

Processor Systems, ARCS, Hannover, Germany, February 22-25, 2010.

• [SORT10] J. Zeppenfeld, A. Bouajila, A. Herkersdorf, W. Stechele. Towards Scalability and

Reliability of Autonomic Systems on Chip, 1st IEEE Workshop on Self-Organizing Real-Time Systems, Carmona, Spain, May 4, 2010.

• [IJCNN10] B. Rakitsch, A. Bernauer, O. Bringmann, W. Rosenstiel. Pruning population size in

XCS for complex problems, International Joint Conference on Neural Networks at the World Congress on Computational Intelligence (WCCI), Barcelona, Spain, July 18-23, 2010.

• [BICC10] A. Bernauer, J. Zeppenfeld, O. Bringmann, A. Herkersdorf, W. Rosenstiel.

Combining software and hardware LCS for lightweight on-chip learning, DIPES/BICC 2010, IFIP AICT 329, p.279-290, Brisbane, Australia, September 20-23, 2010. October 7, 2010 ASoC - Architecture and Design Methodology for SoC