APAC 2007, session 7 Accelerator Technology RRCAT, Indore, India, - - PowerPoint PPT Presentation

apac 2007 session 7 accelerator technology rrcat indore
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APAC 2007, session 7 Accelerator Technology RRCAT, Indore, India, - - PowerPoint PPT Presentation

Lo w-lev el RF Con trol System Design and Ar hiteture La wrene R. Do olittle, LBNL, Berk eley , CA 94720, USA APAC 2007, session 7 Accelerator Technology RRCAT, Indore, India, Jan 28 - Feb 2, 2007


slide-1
SLIDE 1 Lo w-lev el RF Con trol System Design and Ar hite ture La wren e R. Do
  • little,
LBNL, Berk eley , CA 94720, USA

APAC 2007, session 7 ‘Accelerator Technology’ RRCAT, Indore, India, Jan 28 - Feb 2, 2007 http://recycle.lbl.gov/apac2007/ Problems worthy of attack show their worth by hitting back.

  • Piet Hein (1905-1996), Danish polymath
slide-2
SLIDE 2

Analog, Digital, or Hybrid Controller Plant single or multiple cavities ring or linac pulsed or CW normal or superconducting Measurement noise System noise

Σ Σ

slide-3
SLIDE 3
  • 40
  • 20

20 40 60 80 100 1 10 100 1000 10000 100000 1e+06 1e+07 Gain (dB) Frequency (Hz) cavity responses, bandwidths 50 Hz to 50 kHz pole-zero cancelling controller responses

Gain = KP + KI s A complex system that works is invariably found to have evolved from a simple system that worked.

  • John Gall, U.S. author
slide-4
SLIDE 4
  • 40
  • 20

20 40 60 80 100 1 10 100 1000 10000 100000 1e+06 1e+07 Gain (dB) Frequency (Hz)

Gain = KP 1 + sτ + KI s

slide-5
SLIDE 5

Conditioning Signal Conditioning Signal Conditioning Signal

housekeeping and custom functions FPGA

Conditioning Signal

DAC DAC ADC ADC Host CPU or PHY Host I/F Network

The cheapest, fastest and most reliable components

  • f a computer system are those that aren’t there.
  • Gordon Bell (1934-), U.S. computer engineer

Embrace simplicity. Put others first. Desire little.

  • Laozi (4th century BC?), Chinese philosopher
slide-6
SLIDE 6

housekeeping and custom functions FPGA DAC DAC ADC ADC Host CPU or PHY LO Clock Host I/F Network

slide-7
SLIDE 7 Computer FPGA

Programmable digital logic device Yes Yes Major suppliers uncountable 2 Glue-less hookup to most DAQ hardware

  • Yes

Guaranteed low-latency processing

  • Yes

Good programming languages Yes

  • Good programming requires thought and experience

Yes Yes

4-input look-up table Flip Flop

1536 (US$10) to 178176 (US$6000) cells, plus routing, carry chains, multipliers, RAM, input, and output VHDL was written by a bunch of software guys who knew nothing about designing hardware. We beat on it until you could do hardware with it. Verilog was written by a bunch of hardware guys who knew nothing about designing software. We beat on it until you could do software with it. Neither does the job they were originally intended to do, but they work.

  • David Bishop, Engineer

When someone says ‘I want a programming language in which I need only say what I wish done,’ give him a lollipop.

  • Alan Perlis (1922-1990), U.S. computer scientist
slide-8
SLIDE 8

ADC ADC ADC DAC DAC LO LO LO LO LO

RF to Klystron Modulated Calibration Line phase reference Cavity 1 Field Cavity 2 Field

Σ Σ Σ

Be patient, man. I’m trying to be linear.

  • A.L.F., fictional TV alien, 1986-1990
slide-9
SLIDE 9

cavity ADC

CORDIC SetR

DAC to Klystron

Setθ+nωT +

  • A

θ r x y

slide-10
SLIDE 10

cavity ADC

CORDIC SetR

DAC to Klystron phase reference ADC

Phase

Σ

Setθ+nωT

S/H

+

  • A

θ r x y Measure

slide-11
SLIDE 11

Σ

cavity ADC

CORDIC SetR

KP+KI/s

DAC to Klystron phase reference ADC

DDC CORDIC

Σ

Setθ+nωT

S/H

(or predictive filter) θ r x y θ r x y

slide-12
SLIDE 12

Σ Σ

cavity ADC

Setpoint Waveform

1-z-2

DDC

DUC (complex)

Σ

KP+KI/s

DAC to Klystron

DDR output cell z-1 z-1

Σ

z-1 z-1 Σ z-1 z-1

γ δ γ’ δ’

Σ Σ

z-1 z-1 z-1

  • z-1

z-1

Σ

z-1 z-1

Σ

ν

z-1 z-1

Σ

ν

z-1 z-1 z-1

Σ

z-1 z-1

Σ

z-1

Σ

z-1 z-1 ADC z-1 Setpoint Waveform z-1

What’s the difference between hardware and software? Hardware keeps getting cheaper, faster, and smaller.

  • Rick Cochran, U.S. system analyst
slide-13
SLIDE 13 Sim ulations

Test Bench Driver Code Model Physics Model Physics Driver Code Test Bench Language simulator Global Controls FPGA hardware Language simulator code FPGA code FPGA code FPGA with controller Physics Model

slide-14
SLIDE 14

LLRF

Phase Reference High Power RF Interlocks Beam Diagnostics Machine Timing Global Controls Additional mandatory features:

  • cavity detune measurement
  • self-test, self-cal
  • exception handling

It is easier to move a problem around than it is to solve it.

  • Ross Callon, U.S. network engineer
slide-15
SLIDE 15

2001 2006

slide-16
SLIDE 16 Hardw are

ADC ADC ADC DAC DAC LO LO LO LO LO

RF to Klystron Modulated Calibration Line phase reference Cavity 1 Field Cavity 2 Field

Σ Σ Σ

Soft w are

Σ cavity ADC

CORDIC SetR

KP+KI/s

DAC to Klystron phase reference ADC

DDC CORDIC

Σ

Setθ+nωT

S/H

(or predictive filter) θ r x y θ r x y

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away.

  • Antoine de Saint-Exup´

ery (1900-1944), French writer and aviator

slide-17
SLIDE 17 Thank y
  • u
for y
  • ur
atten tion! A kno wledgmen ts

Alex Ratti Brian Chase Mark Champion Taylor Davidson Hengjie Ma Chip Piller Stefan Simrock John Staples Yubin Zhao Image credits: Wikipedia, Wiley Miller This talk is online at http://recycle.lbl.gov/apac2007/ I have only made this letter rather long because I have not had time to make it shorter.

  • Blaise Pascal (1623-1662), French mathematician and philosopher