An Asynchronous Fully Digital DLL for DDR SDRAM Data Recovery Jim - - PowerPoint PPT Presentation

MANCHESTER

1824

The University

• f Manchester

An Asynchronous Fully Digital DLL for DDR SDRAM Data Recovery

Jim Garside et al. University of Manchester

MANCHESTER

1824

The University

• f Manchester

Contents

❏ The problem ❏ Why ‘asynchronous’ ❏ Some asynchronous bits and pieces ❏ Dynamic switching and glitches ❏ Overall system ❏ Results ❏ Critique

MANCHESTER

1824

The University

• f Manchester

The Problem

❏ Want a reliable on-chip delay of clock period ❏ Strobes arrive ‘unexpectedly’ at an arbitrary phase to the internal clock ❏ Did have a 2x clock from which the SDRAM clock was derived

Capture Sync. Delay Data Strobe

SDRAM

❏ Recover data from DDR SDRAM Data Strobe Want:

1 4

MANCHESTER

1824

The University

• f Manchester

Existing solutions

❏ Previous solutions existed ❏ Some (potentially) not as good ❍ e.g. using a fixed delay chain ❏ DLLs relied on (self) calibration before operation ❍ Not adapting dynamically to (e.g.) temperature changes ❏ Not readily available!

MANCHESTER

1824

The University

• f Manchester

Why ‘asynchronous’?

… especially when the system is so synchronous! We looked at the delay problem ourselves: ❍ in ignorance without preconceptions ❍ producing a matched delay seemed like something we knew how to do! ❍ actual delay control is not synchronous with the system clock – not too scary! The result was: ❍ a novel solution ❍ with some useful properties

MANCHESTER

1824

The University

• f Manchester

Delay line

❏ Delays not particularly remarkable ❏ Control adopted from Amulet2e ❍ arbitrarily extensible with three control signals

C C C C L M R

MANCHESTER

1824

The University

• f Manchester

Phase comparator

Operation: ❏ If one request is more than delay′ ahead of the other it wins both mutexes. When the other request arrives an appropriate correction pulse results. ❏ If the requests arrive close to each other (within delay′) lock is achieved. The (fixed) delays provide a window to prevent ‘hunting’.

mutex mutex delay´ delay´ lock inc dec r0 r1

MANCHESTER

1824

The University

• f Manchester

Asynchronous state machine

❏ Modulo up/down counter converts pulses to rolling code

hold L M R slave tristable master tristable decp incp inc dec A B C X Y Z

MANCHESTER

1824

The University

• f Manchester

Switching and glitching

❏ Can the delay be adjusted (safely) whilst in use? ❏ SPICE simulation suggests so ❍ Plot shows worst glitch discovered ❏ Considerable ‘filtering’ provided by subsequent circuits

Switched stage output One stage later Two stages later Control signal (before buffer) 100 ns

V

1.00 1.25 0.75 0.50 0.25 0.00

MANCHESTER

1824

The University

• f Manchester

Overall architecture

❏ One delay line is used for feedback to calibrate DLL ❏ Parallel delay lines are used to delay strobes ❏ Extra delay line provided for fault tolerance ❏ Other logic used for test and calibration

delay lines including spare async. FSM strobes in strobes out test/control redundancy control test

• utputs

individual trimming delays trim control phase detect arbiters reference input encoder delay value

MANCHESTER

1824

The University

• f Manchester

Layout

❏ Hand layout from standard cells ❏ 130 nm process ❏ 630 µm × 25 µm

MANCHESTER

1824

The University

• f Manchester

Test results

❏ Measured from silicon ❏ Wide window of tolerance ❏ Locks in the centre

Stages employed Clock period (ns) 10 20 30 40 10 8 6 4 2 12

133 MHz SDRAM Data recovered Data not recovered ‘max.’ speed ‘automatic’ DLL setting

MANCHESTER

1824

The University

• f Manchester

Potential improvements

Like most designs, by the time it’s made there are some new ideas ❏ Locking window ❍ There is a fixed time ‘window’ in the phase comparator ❍ This could be made programmable to reduce ‘hunting’ around a lock ❏ Power saving ❍ The manufactured DLL is continuously calibrated so a clock runs down one line all the time ❍ This is dumb! Physical conditions change slowly. Once locked the clock need only be sent ‘occasionally’ to confirm or re-establish a lock. ❍ It would be possible to ‘gate off’ edges from the ‘tail’ of the line They currently always run the full length

MANCHESTER

1824

The University

• f Manchester

Conclusions

❏ The circuit works (well) in silicon ❍ Finds ‘best’ delay for required job ❍ Allows continuous calibration ❏ Fully digital solution: all standard cells ❍ (with the addition of a mutex) ❏ Asynchronous ‘mindset’ resulted in ‘unusual’ design ❍ Async. state machine used to solve SDRAM problem ❏ Several inefficiencies in manufactured circuit ❍ There were competing priorities at the time!

MANCHESTER

1824

The University

• f Manchester

Acknowledgements

❏ Co-authors ❍ Steve Furber ❍ Steve Temple ❍ Dave Clark ❍ Luis Plana ❏ Rest of APT group ❏ Sponsors ❍ EPSRC ❍ ARM Ltd. ❍ Silistix