Advanced Channel Engineering Achieving Aggressive Reduction of V T - - PowerPoint PPT Presentation

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Advanced Channel Engineering Achieving Aggressive Reduction of V T - - PowerPoint PPT Presentation

Feb 10, 2023 107 likes •383 views

Advanced Channel Engineering Achieving Aggressive Reduction of V T Variation for Ultra-Low-Power Applications K.Fujita, Y.Torii, M.Hori, J.Oh, L.Shifren*, P.Ranade*, M.Nakagawa, K.Okabe, T.Miyake, K.Ohkoshi, M.Kuramae, T.Mori, T.Tsuruta,

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Advanced Channel Engineering Achieving Aggressive Reduction of VT Variation for Ultra-Low-Power Applications

K.Fujita, Y.Torii, M.Hori, J.Oh, L.Shifren*, P.Ranade*, M.Nakagawa, K.Okabe, T.Miyake, K.Ohkoshi, M.Kuramae, T.Mori, T.Tsuruta, S.Thompson*, T.Ema Fujitsu Semiconductor Ltd. *SuVolta Inc.

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Outline

  • Introduction
  • Transistor Structure
  • Features of Process Flow and

Verification

  • 65nm 6T-SRAM Evaluation Results
  • Summary
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Introduction

 complicated

Power crisis

VDD lowering VT variation RDF ETSOI, Tri-gate Alternative solution

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Transistor structure

Deeply Depleted Channel TM (DDC) Transistor 1 2 3 4 Depleted layer VT setting offset layer Screening layer Anti-punch-through layer

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Process flow

Well Implant VT / Screen Layer Implant Blanket Si Epi-layer Formation STI Formation Gate Dielectric Formation for HV Gate Dielectric Formation for LV Poly-Si Gate Formation Extension Implant (No Halo) SW Formation S/D Formation 1 2 3

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TEM of DDC transistor

43.1nm

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Uniformity of epitaxial silicon

7

  • Avg. = 27.2nm, 1sigma = 0.25%
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TEM of low-temperature STI

S D

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  • 0.5
  • 0.4
  • 0.3
  • 0.2
  • 0.1

0.1 0.2 0.3 0.4 0.5 0.1 1 10 Gate Width [m] VT [V]

W-dependence of VT

NMOS PMOS L=0.045m

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NMOS PMOS

I-V characteristics

L=0.045m |Vdd|=0.9, 0.1V

1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02

  • 1.5
  • 1.0
  • 0.5

0.0 0.5 1.0 1.5 Vg [V] Id [A/m]

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Summary of STI

11

  • Excellent STI profile
  • No anomalous W dependence
  • Nice sub-threshold characteristics

No concern about low temp. STI

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Breakdown of low-temperature GOX

  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1

1 2 3 2 3 4 5 6 Breakdown Voltage [V] LN(-LN(1-F))

L=0.045m Sg=1E-7cm2

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NBTI of DDC PMOS

10 years

1E+00 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 1E+10 1 10 Vstress [V] Lifetime@Id-10% [sec]

2 3 4 5

T=125ºC L=0.045m

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HCI of DDC

1E+00 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 1E+10 Lifetime@Id-10% [sec] 1/Vdd [1/V]

  • 1

1

  • 0.5

0.5 AC 10 years @ Duty 2% NMOS PMOS T=25ºC L=0.045m

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Summary of GOX

  • Excellent distribution of breakdown
  • Long enough life time for NBTI
  • Long enough life time for HCI

No concern about low temp. GOX

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VT distribution of NMOS

  • 3
  • 2
  • 1

1 2 3 0.2 0.4 0.6 0.8 Pull-down VT [V] Cumulative Probability []

  • 3
  • 2
  • 1

1 2 3 0.2 0.4 0.6 0.8 Pass-gate VT [V] Cumulative Probability []

Baseline Baseline DDC DDC

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VT distribution of PMOS

  • 3
  • 2
  • 1

1 2 3

  • 0.8
  • 0.6
  • 0.4
  • 0.2

Pull-up VT [V] Cumulative Probability []

, Baseline , DDC

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0.00 0.02 0.04 0.06 0.08

  • 0.8
  • 0.4

0.4 0.8 VT [V] VT across wafer [V]

Baseline (pull-down) Baseline (pass-gate) Baseline (pull-up) DDC (pull-down) DDC (pass-gate) DDC (pull-up)

Summary of across-wafer variation

Baseline DDC

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  • 3
  • 2
  • 1

1 2 3

  • 0.2
  • 0.1

0.1 0.2 Pass-gate VT [V] Cumulative Probability []

  • 3
  • 2
  • 1

1 2 3

  • 0.2
  • 0.1

0.1 0.2 Pull-down VT [V] Cumulative Probability []

VT matching of NMOS

Baseline DDC Baseline DDC

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VT matching of PMOS

  • 3
  • 2
  • 1

1 2 3

  • 0.2
  • 0.1

0.1 0.2 Pull-up VT [V] Cumulative Probability [] Baseline DDC

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Summary of VT matching

Baseline DDC 0.00 0.02 0.04 0.06 0.08

  • 0.8
  • 0.4

0.4 0.8 VT [V] VT / SQRT(2) [V]

Baseline (pull-down) Baseline (pass-gate) Baseline (pull-up) DDC (pull-down) DDC (pass-gate) DDC (pull-up)

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0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 Node 1 [V] Node 2 [V]

0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 Node 1 [V] Node 2 [V]

Butterfly curves of 6T-SRAM

Baseline DDC

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SNM distribution

  • 5
  • 4
  • 3
  • 2
  • 1

1 2 3

  • 100

100 200 SNM [mV] Cumulative Probability [] Baseline DDC

Vdd=0.4V

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Vdd dependence of SNM

1 2 3 4 5 6 7 8 9 10 0.0 0.2 0.4 0.6 0.8 1.0 Vdd [V] SNM (mean/1σ) [σ] Baseline DDC

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Vddmin of 576K bit SRAM array

0.0 0.2 0.4 0.6 0.8 1.0 Vdd [V] Baseline DDC

100 80 60 40 20 Yield of SRAM macro [%]

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Summary

  • Deeply Depleted Channel (DDC) transistor

has been introduced to reduce RDF.

  • Process flow of DDC has been established.
  • VT matching of SRAM has been reduced to

less than half by DDC.

  • Near to 0.4V operation of SRAM has been

achieved.