LIGO-G050318-00-C
AdL SUS/US Quad Controls Conceptual Design
- J. Heefner
AdL SUS/US Quad Controls Conceptual Design J. Heefner 7/12/2005 - - PowerPoint PPT Presentation
AdL SUS/US Quad Controls Conceptual Design J. Heefner 7/12/2005 LIGO-G050318-00-C AdL SUS Controls Conceptual Design Design Considerations AdL Controls Architecture has yet to be determined Controls block diagram based on scaling
LIGO-G050318-00-C
AdLIGO 2
LIGO-G050318-00-C
– Controls block diagram based on scaling of existing LIGO controls and architecture along with present DSpace controls
– Requirements for ADC input noise based on recent testing of the Analog Devices AD7679 – Requirements for DAC output noise based on experience with the VME-based Frequency Devices DAC module – Requirements for Binary I/O based on experience with VME, PCI and PC104 based binary I/O modules
AdLIGO 3
LIGO-G050318-00-C
The requirements for the system can be found in the Universal
Highlights of electronics requirements:
» ADC-
– Input Voltage: +/-10 volts, differential – Input Impedance: >1Kohm – Input-referred noise: <200nV/√Hz for freq>100Hz, 200nV/√Hz @10Hz[1] – Sample Rate: 16384 samples/second, nominal – CMRR: >68dB at 100KHz [1] The numbers for the input referred noise voltage of the ADC are based on tests recently conducted on the Analog Devices AD7679 ADC. In these tests, it was found that the input referred noise voltage of the ADC is less than 100nV/√Hz for freq>10Hz, but the input range was +/-5 Volts.
AdLIGO 4
LIGO-G050318-00-C
– Output Voltage: +/-10 volts, differential – Drive capability: 1Kohm load shunted by 1000pF capacitance – Output-referred noise: 200nV/√Hz for freq>100Hz, TBD @10Hz[1] – Sample Rate: 16384 samples/second, nominal [1] Output noise voltage for DACs is based on measured output noise of the present LIGO VME-based DACs manufactured by Frequency Devices.
– Switching Voltage: 5 volts minimum, 30 volts maximum – Switching Current: 1 amp maximum – Switching Time: < 1milli-seconds – On-state voltage: 2 volts maximum
AdLIGO 5
LIGO-G050318-00-C
– On-State voltage (logical 1): > 2 volts – Off-state voltage (logical 0): <0.8 volts – Maximum input voltage: TBD – Input impedance: >1Kohm
– The state of a circuit must be capable of being read back to the controlling hardware. The success of all binary instructions to a module from CDS must be verifiable via a return signal derived from the controlled hardware.
– Shielded-twisted pairs – Coax
AdLIGO 6
LIGO-G050318-00-C
AdLIGO 7
LIGO-G050318-00-C
SEI Input Optics (IO) & Output Optics Quad SUS
φ
Mix I/F PD
RF Osc.
I/F PD I/F PD MODULATION DETECTION DETECTION MODE CONTROLLER ACQUISITION MODE CONTROLLER MODE SWITCHING ALGORITHM SUS CPU SUS ADC SUS DAC Local Control DeWh Filters AI Filters I/F Reflected Memory? I/F Reflected Memory? UIM DeWh Filters Penultimate DeWh Filters ESD DeWh Filters AI Filters AI Filters AI Filters Local Control Wh Filters AA Filters Coil Drivers (6) Coil Drivers (6) Coil Drivers (6) Coil Drivers (6) ES Drivers UPPER MASS UIM PM TM
12 12 4 4 5
ISC Global Actuator ISC Global Actuator ISC Global Actuator SUS Local Actuator PSL IO/IMC DAQ GDS 5 BSC Systems per IFO 6 HAM Systems per IFO SUS/UK per IFO: ETMx, ETMy (quads) ITMx, ITMy (quads) FMx, FMy (triple; folded IFO only) BS (triple) SUS/US per IFO: PRM (triple) SRM (triple) IMC2 (triple) OMC (TBD) Cabling from Drivers to Vacuum Chamber Feed- Throughs is SUS/US Responsibility Cabling from Vacuum Chamber Feed-Throughs to SUS I/F Connector & Bracket is SEI Responsibility OSEM Sensor I/F
SUS/US SUS/UK
ISC AND SUS INTERFACE BLOCK DIAGRAM
ISC
Digital I/O
φ
Mix Mix
φ
CONTROLLERS SUPERVISORY CONTROL Timing System Network Packaging & Channels per Module are TBD Packaging & Channels per Module are TBD Φ = Phase adjuster PD = PhotoDiode I/F = Interface AI = Anti-Image Filter AA = Anti-Alias Filter DeWh = De-Whitening Filter Wh = Whitening Filter ES = Electro-Static UIM = Upper Intermediate Mass PM = Penultimate Mass TM = Test Mass Optical Radio Frequency (RF) Control/Monitor Audio Frequency (AF)
AdLIGO 8
LIGO-G050318-00-C
– OSEMs – OSEM LED drive and PD readback electronics – OSEM Coil Drive electronics – Electro-Static Drive electronics
– All vacuum cabling and connectors required to propagate signals to/from OSEMs and ESD actuators – All external cable and connectors – Power supplies – All anti-alias, whitening, anti-image, dewhitening, etc to match to ADCs and DACs.
AdLIGO 9
LIGO-G050318-00-C
– All ADCs, DACs, BIO required – All computing hardware and software required – All networking hardware and software required – Racks and subracks, TBD depending on location of equipment
AdLIGO 10
LIGO-G050318-00-C
AdLIGO 11
LIGO-G050318-00-C
AdLIGO 12
LIGO-G050318-00-C
AdLIGO 13
LIGO-G050318-00-C
AdLIGO 14
LIGO-G050318-00-C
stages are each roughly equivalent to what is presently required for a single LIGO LOS.
quad is approx. equivalent to 4 LIGO LOS’s.
system with our existing controls architecture, if needed. We could also use a variation of some of the PCI-based controls that has been used recently.
AdL CDS design.
Input Matrix (6x6) 6 CH
M0 L3
From ISC Global Controls FM 6 CH Output Matrix (6x6) 6 DOF FM 6 DOF 6 CH Input Matrix (6x6) 6 CH
R0
FM 6 CH Output Matrix (6x6) 6 DOF FM 6 DOF 6 CH Input Matrix (4x3) 4 CH
L2
FM 4 CH Output Matrix
(3x4) 12 FMs 3 DOF FM 3 DOF 4 CH Output Matrix (3x5) 3 DOF FM 3 DOF 5 CH FM 6 CH FM 6 CH FM 4 CH FM 5 CH From ISC Global Controls
+
3 DOF FM Input Matrix (4x3) 4 CH
L1
FM 4 CH Output Matrix
(3x4) 12 FMs 3 DOF FM 3 DOF 4 CH FM 4 CH From ISC Global Controls
+
3 DOF FM
Total Number of filter modules = 18+18+26+26+8=96 Total ADC inputs = 6+6+4+4=20 Total DAC outputs = 6+6+4+4+5=25
Control BW= 0.1Hz-3Hz Control BW= 3Hz-30Hz Control BW= 30Hz-300Hz
AdLIGO 15
LIGO-G050318-00-C
» Prototypes for the vacuum harnesses and cables are being fabricated for use on the quad test stand at CIT. » Additional cables and harnesses will be fab’d for LASTI » AdL SEI is using the same types of cables, connectors and conventions as AdL SUS
AdLIGO 16
LIGO-G050318-00-C
» Cable diagrams per the ICD have been generated for a LASTI implementation » AA, whitening, AI, dewhitening TBD pending selection of ADC, DACs, BIO for LASTI controls » AdL CDS architecture designs are in progress and should converge prior to LASTI need
controls (not DSpace). These controls would then be integrated with the AdL SEI controls and the existing LASTI infrastructure.
A1 A2 A3 A4 A5 A6 A7 A8 A9 A Shield C1 C2 C3 C4 C5 C6 C7 C8 C9 C Shield E1 E14 E2 E15 E3 E16 E4 E17 E5 E18 E6 E19 E7 E20 E8 E21 E9 E22 E10 E23 E11 E24 E12 E25 E13 Male Female Micro Female Micro B1 B2 B3 B4 B5 B6 B7 B8 B9 B Shield Female Micro D1 D2 D3 D4 D5 D6 D7 D8 D9 D Shield Female Micro CAB_? Shield 1 ST Coil 2 NC 3 LED-A 4 PD-A 5 FN Coil 6 NC 7 LED-K 8 PD-K 9 AdL OSEM Micro D Male XXX? Shield 1 ST Coil 2 NC 3 LED-A 4 PD-A 5 FN Coil 6 NC 7 LED-K 8 PD-K 9 AdL OSEM Micro D Male XXX? Shield 1 ST Coil 2 NC 3 LED-A 4 PD-A 5 FN Coil 6 NC 7 LED-K 8 PD-K 9 AdL OSEM Micro D Male XXX? Shield 1 ST Coil 2 NC 3 LED-A 4 PD-A 5 FN Coil 6 NC 7 LED-K 8 PD-K 9 AdL OSEM Micro D Male XXX? B1 B14 B2 B15 B3 B16 B4 B17 B5 B18 B6 B19 B7 B20 B8 B21 B9 B22 B10 B23 B11 B24 B12 B25 B13 A1 A14 A2 A15 A3 A16 A4 A17 A5 A18 A6 A19 A7 A20 A8 A21 A9 A22 A10 A23 A11 A24 A12 A25 A13 B Shield A Shield Female Female XXX-XX VAC CABLE 25 PIN V1 V14 V2 V15 V3 V16 V4 V17 V5 V18 V6 V19 V7 V20 V8 V21 V9 V22 V10 V23 V11 V24 V12 V25 V13 A1 A14 A2 A15 A3 A16 A4 A17 A5 A18 A6 A19 A7 A20 A8 A21 A9 A22 A10 A23 A11 A24 A12 A25 A13 VACUUM AIR XXXX VACUUM FEEDTHRU 25A 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 13A 14A 15A 16A 17A 18A 19A 20A 21A 22A 23A 24A 1B 2B 3B 4B 5B 6B 7B 8B 9B 10B 11B 12B 13B 14B 15B 16B 17B 18B 19B 20B 21B 22B 23B 24B 25B Sh A Sh B XXXX SHIELDED 25 CONDSeismic Table
DB25 DB25 DB25 PD-K D J1-14 LED-A D J1-2 LED-K D J1-15 ST Coil D J1-3 FN Coil D J1-16 PD-A C J1-4 PD-K C J1-17 LED-A C J1-5 LED-K C J1-18 ST Coil C J1-6 FN Coil C J1-19 PD-A B J1-7 PD-K B J1-20 LED-A B J1-8 LED-K B J1-21 ST Coil B J1-9 FN Coil B J1-22 PD-A A J1-10 PD-K A J1-23 LED-A A J1-11 LED-K A J1-24 ST Coil A J1-12 FN Coil A J1-25 Shield J1-13 PD-A D J1-1 Female OSEM A OSEM B OSEM C OSEM D UK SUS Satellite Module Sensor A- J2-14 ST Coil A J2-2 FN Coil A J2-15 Sensor B+ J2-3 Sensor B- J2-16 ST Coil B J2-4 FN Coil B J2-17 Sensor C+ J2-5 Sensor C- J2-18 ST Coil C J2-6 FN Coil C J2-19 Sensor D+ J2-7 Sensor D- J2-20 ST Coil D J2-8 FN Coil D J2-21 +17V In J2-9 RTN J2-22 +17 Vin J2-10 RTN J2-23Vacuum Flange
AdLIGO 17
LIGO-G050318-00-C
Monitors
» In LIGO we had auxiliary monitors for:
– Coil driver output current, rms current, output voltage, current fault – OSEM PD voltage – Many others- We tended to err on the side of overkill
Mode Switches and readbacks for coil drivers and ESD
» In LIGO we had switches for:
– Coil Driver Run/Acquire, Coil Driver Test input enable, Coil Driver enable – Whitening and dewhitening enable
Test inputs and test monitors AC vs. DC drive of ESD Interlocks and watchdogs