Accelerate Cycle-Level Multi-Core RISC-V Simulation with Binary - - PowerPoint PPT Presentation

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Accelerate Cycle-Level Multi-Core RISC-V Simulation with Binary - - PowerPoint PPT Presentation

Sep 12, 2022 550 likes •794 views

Accelerate Cycle-Level Multi-Core RISC-V Simulation with Binary Translation Xuan Guo, Robert Mullins Department of Computer Science and Technology Both the paper and the slides are made available under CC BY 4.0 Motivation We want to

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SLIDE 1

Accelerate Cycle-Level Multi-Core RISC-V Simulation with Binary Translation

Xuan Guo, Robert Mullins Department of Computer Science and Technology Both the paper and the slides are made available under CC BY 4.0

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SLIDE 2

Motivation

  • We want to evaluate processor designs with meaningful workloads
  • Not just microbenchmarks
  • Existing simulators are too slow for the task
  • Last year we looked at TLB simulation:
  • Fast TLB Simulation for RISC-V Systems @ CARRV 2019
  • We based the work on top of QEMU
  • For TLB design, we don’t really need cycle accuracy
  • The assumption does not hold for cache simulation!
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SLIDE 3

Design Goals

  • Full-system capable
  • With the presence of an operating system
  • Cycle-level simulation
  • Ability to model multicore interaction
  • Include cache coherency and shared caches
  • Fast!
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SLIDE 4

R2VM

  • Rust RISC-V Virtual Machine
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SLIDE 5

Design

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SLIDE 6

Prior Art

  • Igor Böhm, Björn Franke, and Nigel Topham. 2010. Cycle-accurate

performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator.

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SLIDE 7

From Single-Core to Multi-Core

  • We have an accurate single-core cycle-level simulator
  • We instantiate multiple copies of it in parallel
  • Assume each single-core simulator is thread safe already
  • What could go wrong?
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SLIDE 8

Multi-Core Interaction

  • Prone to distortion from the host
  • OS scheduler
  • Length of JITed code
  • Multithreading
  • Cannot model interaction within the guest
  • Single-writer-multiple-reader cache coherency
  • Micro-contention
  • Etc
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SLIDE 9

Lockstep Execution

  • Need to keep simulated cores in sync
  • So we need to have them run in lockstep
  • Hard with binary translation
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SLIDE 10

A Failed Attempt

Thread 0 Core 0 Inst 1 Core 0 Inst 2 Core 0 Inst 3 … Thread 1 Core 1 Inst 1 Core 1 Inst 2 Core 1 Inst 3 … Thread N Core N Inst 1 Core N Inst 2 Core N Inst 3 … … Thread Barrier Thread Barrier Thread Barrier

std::sync::Barrier 100k/s Spinning 1M/s

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SLIDE 11

Lockstep Execution

  • Need to keep simulated cores in sync
  • So we need to have them run in lockstep
  • Hard with binary translation
  • Thread barriers are slow and do not scale.
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SLIDE 12

Fiber/Coroutine

  • Yield control within a function
  • We use stackful fibers
  • Boost::Coroutine is stackful
  • Goroutines are stackful
  • Most modern languages use stackless
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SLIDE 13

Fiber

  • How is it implemented (traditional approach):
  • Get the current fiber from TLS
  • Save registers of current fiber
  • Switch to the next fiber and set TLS
  • Switch the stack to the new fiber’s
  • Restore registers from the new fiber
  • Restore execution
  • 50M yields/second
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SLIDE 14

Fiber

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SLIDE 15

Fiber

  • How is it implemented (traditional approach):
  • Get the current fiber from TLS
  • Save registers of current fiber
  • Switch to the next fiber and set TLS
  • Switch the stack to the new fiber’s
  • Restore registers from the new fiber
  • Restore execution
  • 50M yields/second
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SLIDE 16

Fiber

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SLIDE 17

Fiber

  • How is it implemented (traditional approach):
  • Get the current fiber from TLS
  • Save registers of current fiber
  • Switch to the next fiber and set TLS
  • Switch the stack to the new fiber’s
  • Restore registers from the new fiber
  • Restore execution
  • 50M yields/second
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SLIDE 18

Fiber

  • fiber_yield_raw:

mov [rbp - 32], rsp ; Save current stack pointer mov rbp, [rbp - 16] ; Move to next fiber mov rsp, [rbp - 32] ; Restore stack pointer ret

  • 80-90M yields/second
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SLIDE 19

Memory Simulation

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SLIDE 20

Memory Access Flow

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SLIDE 21

Performance

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SLIDE 22

Open Source

  • https://github.com/nbdd0121/r2vm
  • MIT/Apache-2.0 Dual Licensed
  • Not GPL!