- A Tutorial - Based on Slides from Dr. Bibhudatta Sahoo University - PowerPoint PPT Presentation

Thermal Noise Consideration (1) Signal-to-noise ratio of an ADC is given by,  𝑸 𝒕𝒋𝒉 𝑻𝑶𝑺 = 𝟐𝟏𝒎𝒑𝒉 𝟐𝟏 𝑹 𝑶 +𝑶 𝑼 where, 𝟑 𝑾 𝒒−𝒒 𝑾 𝒒−𝒒 P sig = signal power = (for input 𝑾 𝒋𝒐 = 𝒕𝒋𝒐 𝟑𝝆𝒈𝒖 )  𝟗 𝟑 𝑹 𝑶 = 𝜠 𝟑 𝟐𝟑 ,  𝑶 𝑼 = Input referred thermal noise power of the ADC  𝑾 𝒒−𝒒 𝜠 = 𝟑 𝑶 , where N = ADC resolution.  SNR of Semiconductor ADCs are limited by thermal noise of:  Switches  Op amps  Switch thermal noise can be minimized by using large capacitors. The thermal noise of the  switches is given by “ 𝒍𝑼/𝑫 ”, where 𝒍 = 𝟐. 𝟒𝟗 × 𝟐𝟏 −𝟑𝟒 , 𝑼 = Temperature in 𝑳 , and 𝑫 is the sampling capacitor. Op amp thermal noise can be minimized by burning more current.  Slides by Bibhudatta Sahoo -21- 21

Thermal Noise Consideration (2)  It is costly in terms of power, area, and speed to make input thermal noise smaller than quantization noise for ADC resolution, 𝑶 > 𝟐𝟏  bits.  For example: If full-scale ADC input is 1 V, then for a 11-bit ADC the quantization noise power is given by: 𝟑 𝟑 𝑾 𝑴𝑻𝑪 𝟐 𝟐 = 𝟐𝟓𝟐𝝂𝑾 𝒔𝒏𝒕 𝟑  𝑹 𝑶 = 𝟐𝟑 = 𝟑 𝟐𝟏 𝟐𝟑  If thermal noise voltage power ( 𝑶 𝑼 ) is same as quantization noise power then the SNR takes a 𝟒 dB hit. 𝑹 𝑶  If SNR has to take < 𝟐 dB hit then the 𝑶 𝑼 ≤ 𝟐𝟏 .  Size of the capacitor required to achieve this for 𝟐𝟐 − bit system is 𝟑 𝒒𝑮 .  For a 12-bit system the capacitor required would be 𝟗 𝒒𝑮 (a large value).  For a 16-bit system the capacitor size would be 𝟑 𝒐𝑮 (almost physically unrealizable on chip). Slides by Bibhudatta Sahoo -22- 22

Thermal Noise Consideration (3)  Ignoring other noise sources if thermal noise is only modeled by 𝒍𝑼/𝑫 then the SNR if given by: 𝑸 𝒕𝒋𝒉 𝑻𝑶𝑺 = 𝟐𝟏𝒎𝒑𝒉 𝟐𝟏 𝑹 𝑶 + 𝒍𝑼 𝑫 SNR Vs Capacitance (Full Swing = 1V) SNR Vs Capacitance (Full Swing = 2V) 100.00 100.00 95.00 95.00 90.00 90.00 85.00 8-bit SNR (dB) 85.00 SNR (dB) 80.00 10-bit 80.00 75.00 75.00 12-bit 70.00 70.00 14-bit 65.00 65.00 16-bit 60.00 60.00 55.00 55.00 1.00E-13 1.00E-12 1.00E-11 1.00E-10 1.00E-09 1.00E-13 1.00E-12 1.00E-11 1.00E-10 1.00E-09 Capacitance Capacitance Slides by Bibhudatta Sahoo -23- 23

Distribution of Thermal Noise  Each stage contributes to the thermal noise.  How do we distribute the thermal noise so that the overall input- referred thermal noise is minimized to maximize the SNR?  Lets consider a pipelined ADC built using 1-bit stages (MDAC gain = 2)  Considering only 𝒍𝑼/𝑫 sampled noise the total input referred noise power: 𝟐 𝟐 𝟐 𝟐 𝑶 𝑼 ∝ 𝒍𝑼 𝑫 𝟐 + 𝟑 𝑫 𝟑 + 𝟑 𝑫 𝟒 + ⋯ + 𝟑 𝑯 𝟑 𝟑 ⋯𝑯 𝑶−𝟐 𝟑 𝑯 𝟐 𝑯 𝟐 𝑯 𝟐 𝑫 𝑶 Slides by Bibhudatta Sahoo -24- 24

Stage Scaling for Optimal Noise (1) 𝟐 𝟐 𝟐 𝟐 𝑶 𝑼 ∝ 𝒍𝑼 𝑫 𝟐 + 𝟑 𝑫 𝟑 + 𝟑 𝑫 𝟒 + ⋯ + 𝟑 𝑯 𝟑 𝟑 ⋯𝑯 𝑶−𝟐 𝟑 𝑯 𝟐 𝑯 𝟐 𝑯 𝟐 𝑫 𝑶  If 𝑫 𝟐 = 𝑫 𝟑 = ⋯ 𝑫𝑶 then backend stages contribute very little noise Wasteful as power ∝ 𝑯 𝒏 ∝ 𝑫   How about scaling by 𝟑 𝑵 where 𝑵 is the resolution of each stage.  Same amount of noise from each stage.  Power can be reduced. Slides by Bibhudatta Sahoo -25- 25

SHA-less Architecture  Any mismatch between the “main  1 Main Sampling Path sampling path” and “flash ADC path” results in different voltages · · being sampled on “ 𝑫 ” and “ 𝑫/𝜷 ”.  1 C · · ·  The mismatch can be translated to  1  2 time-constant mismatch (  ). · V IN  For a signal of amplitude “ 𝑩 ” and C/  frequency “ 𝒈 𝒋𝒐 ” the difference in · · voltage sampled on “ 𝑫 ” and “ 𝑫/  ”  1  2 is:   𝑾 = 𝟑  𝒈 𝒋𝒐 𝑩  Flash ADC Path Elements that can have mismatch  Match the flash and MDAC paths. [Mehr 2000] 26 Slides by Bibhudatta Sahoo -26-

Pipeline ADC - Area, Power, Speed, Resolution Optimization- Slides by Bibhudatta Sahoo -27- 27

Pipeline ADC – Area, Power, Speed, Resolution Trade-off Stage-1 r i + Backend · V IN 2 N 1 ADC - · sub-ADC sub-DAC (P-N 1 )-bits (N 1 +1)-bits D BE D 1 2 -N 1 Digital Combiner P-bits D OUT  For a given ADC resolution, the number of stages and number of bits resolved in each stage determines:  power consumption  area 28 Slides by Bibhudatta Sahoo -28-

1.5-bit Stage  2   +V REF C F 1 1 · · · · V IN  C S V X 1 · · · · C X V OUT V  REF   2 1 2 V ´  REF ±V REF ,0 4 Offset 0   Correction   C C V kC V Range  S F IN S REF V V   OUT   ´  kC C C REF    S X F C 4 F   A V  REF Feedback factor = ½.  2 Offset correction range = ± V REF /4 (i.e. ± 150 mV for V REF =0.6V).  Settling Requirement on the op amp reduced by 1-bit.  Input referred noise = ½ of output noise.  -V REF 29 Slides by Bibhudatta Sahoo -29-

2.5-bit Stage  Feedback factor =1/4.  2 Offset correction range +V REF   C 1 1 · ·  = ± V REF /8 (i.e. ± 75 mV for 2 · V REF =0.6V).   C 2 1 1 · · · · ´ Settling Requirement on  V   C 3 REF 1 · · · the op amp reduced by ´ 2 0  b 2-bits. 2 V X ´ · · ±V REF Input referred noise is ¼  C X  Offset C 4 · 0 V OUT 1 · · · · Correction of output noise. V IN ´ Range 1  b 2 Input-Output transfer  ´ function is: ±V REF V  REF · 8 5 C 1 = C 2 = … C 8    2 ´ ·  C V C b V  · i IN i 3 i REF  C 8 1   · · i 1 i 0 V   OUT C C C 5     b 1 2 X C C 1 2 -V REF 1 2 A ±V REF 30 Slides by Bibhudatta Sahoo -30-

3.5-bit Stage  2 Feedback factor = 1/8.  +V REF  C 1 Offset correction range 1  · ·  2 · = ± V REF /16 (i.e. ± 37.5 mV ´   for V REF =0.6V). C 2 1 1 ´ · · · · ´ V Settling Requirement on    C 3 REF 1 · · · ´ 2 the op amp reduced by 0  ´ b 3-bits. 2 ´ V X · · ±V REF ´ Offset Input referred noise is C X   C 4 · 0 V OUT 1 Correction · · · · ´ V IN 1/8 of output noise. Range 1  ´ b 2 Input-Output transfer  ´ function is: ±V REF ´ V  REF · ´ C 1 = C 2 = … C 16 2 · 16 13     ´ C V C b V ·   i IN i 3 i REF C 16 ´ 1   · · i 1 i 0 V   OUT C C C   13   1 2 X b C C 1 2 1 2 -V REF A ±V REF 31 Slides by Bibhudatta Sahoo -31-

Architecture Summary Summary of ADC Stage Architectures 1.5-bit Stage 2.5-bit Stage 3.5-bit Stage Parameter effected Feedback Factor Speed and Power 1 1 1 2 4 8    Offset Correction Linearity of ADC V 4 V 8 V 16 REF REF REF Range Reduction in Settling 1-bit 2-bits 3-bits Speed and Power Requirement Noise Scaling SNR, Power, & 1 1 1 2 4 8 Area Reduction in Capacitor Matching 1-bit 2-bits 3-bits Power and Area Requirement  For resolutions more than 10-bits it is better to resolve more bits in the first stage:  relaxing op amp settling.  capacitor matching.  reducing capacitance  input referred noise is reduced.  DOES NOT relax the op amp open loop DC gain requirement (more later). 32 Slides by Bibhudatta Sahoo -32-

Why not resolve more bits in 1 st Stage? Any mismatch between the “main sampling   1 path” and “flash ADC path” results in Main Sampling Path different voltages being sampled on “C” and “C/  ”. · ·  1 The mismatch can be translated to time- C  · · · constant mismatch (  ).  1  2 The difference in voltage should be within  · V IN the offset correction range of the Flash ADC. Resolving more bits in the 1 st stage reduces  C/  the offset-correction range and hence could · · result in missing codes.  1  2 Offset correction range should include:  Comparator offsets in the flash.  Time constant mismatch (  ).  Flash ADC Path For a signal of amplitude “ A ” and frequency Elements that  can have mismatch “ f in ” the difference in voltage sampled on “C” and “C/  ” is:   V=2  f in A  33 Slides by Bibhudatta Sahoo -33-

DC Gain Requirement of op amp in each stage Stage-1 r i + Backend Residue voltage V ri has to settle to LSB/2 V IN · 2 N 1  ADC - of the backend-ADC. · sub-ADC sub-DAC Gain error:  (P-N 1 )-bits (N 1 +1)-bits D BE D 1 V 1 1   e   2 -N 1     P N 1 V 1 A 2 1 ideal DC Digital Combiner P-bits Resolution reduces but the feedback  D OUT factor also reduces by the same amount  DC gain is defined by the resolution of the ADC and not the resolution of the backend ADC that follows. V e V ri The above holds true for the op amps in  the later stages of the pipeline. t 34 Slides by Bibhudatta Sahoo -34-

Architecture Optimization (1) Some expressions used for architecture optimization i.e. number of pipeline  stages and number of bits/stage: Settling time for N- bit accuracy:        ·  · t settle N 1 ln 2 Two stage op amp poles and unity gain bandwidths:  1 g g         ·  m 2 m 1 , , , and 5 p 1 p 2 u p 2 u R g R C C C 1 m 2 2 C L C Variance of input referred sampled noise:    N kT kT 1    ·        2 2 2 2   2 IN op ref jitter 2   C C G   i 2 1 i i 1 where, C i = sampling caps in each stage, and G i = gain of each stage. 2 nd stage of the op amp is a common source stage. For maximum output swing at  the highest speed typical gain in the 2 nd stage is  10. Overdrive voltage to maximize swing is chosen to be around V OV =150 mV and  hence current in each branch in the two stages are I D1 = g m1 · V OV /2 and I D2 = g m2 · V OV /2 . Slides by Bibhudatta Sahoo -35- 35

Architecture Optimization (2)  Signal swing = ± 750 mV for 1.5 V supply  Resolution = 12-bits (determines quantization noise)  𝒈 𝑵𝑩𝒀, 𝑱𝑶 = 100 MHz  𝒈 𝑻 = 200 MHz  𝒖 𝒕𝒎𝒇𝒙𝒋𝒐𝒉 = 0.5 ns  𝒖 𝒐𝒑𝒐 − 𝒑𝒘𝒇𝒔𝒎𝒃𝒒 = 0.2 ns  𝒖 𝒕𝒇𝒖𝒖𝒎𝒋𝒐𝒉 = 1.8 ns  Noise Budget:  Quantization Noise  Sampled Thermal Noise  Op amp Noise  Reference Noise  Jitter Noise  Input signal buffer Noise Slides by Bibhudatta Sahoo -36- 36

Architecture Optimization (3) Jitter Specification  The variance of jitter voltage is given by:   2  t f A jitter j in where, t j = variance of jitter. f in = frequency of the input signal. A = amplitude of the input signal.  For maximum input frequency of 100 MHz and jitter limited SNR of 80 dB the required rms jitter is 700 fs . Slides by Bibhudatta Sahoo -37- 37

Architecture Optimization (4) Noise Budget Noise Budget LSB (  ) V 1 . 5  p  p = 366 µ V 12 12 2 2 90 µ V Reference Noise 120 µ V Op Amp Noise 64 µ V (2 pF) Sampled Noise (kT/C) Jitter Noise  66 µ V (200 fs RMS jitter) ( ) 2 t f V / 2  j in p p Overall SNR 67.8 dB (in 100 MHz band) Slides by Bibhudatta Sahoo -38- 38

Architecture Optimization (5) Sl. No. Architecture Sampling Capacitance Power Capacitor switching to (mW) (pF) Reference (pF) 1 9, 1.5-bit stages, 3-bit flash 3.0 4.0 138 2 4, 2.5-bit stages, 4-bit flash 1.5 2.5 120 3 3, 3.5-bit stages, 3-bit flash 1.0 2.0 140 2.5-bit 1 st stage, 6, 1.5-bit 4 2.0 2.5 77 stages, and 4-bit flash 3.5-bit 1 st stage, 5, 1.5-bit 5 1.0 1.5 50 stages, and 4-bit flash  Optimization based on the following:  V in(p-p)(diff) =1.5 V  Quantization noise is at 12-bit level.  Thermal noise limited to 66 dB in 100MHz band.  Architecture 5 is optimal. Slides by Bibhudatta Sahoo -39- 39

Calibration : A Necessity Slides by Bibhudatta Sahoo -40- 40

Why Calibrate? Basic Pipeline Stage  As technology scales it is difficult to get:  get high op amp gain to 1. remove gain error 2. suppress nonlinearity  low op amp offset.  capacitor matching to remove DAC nonlinearity.      ( N 1 ) 3 1 2  For example, op amp gain in a 12-bit  A   1 ( N 1 ) system should exceed 12000  81 dB. 2 Slides by Bibhudatta Sahoo -41- 41

Current ADC Design Trends Choose capacitors to satisfy kT/C noise, not  matching. Choose op amp with high swing   kT/C noise relaxed  power consumption reduced.  Relaxes op amp linearity requirement Choose best trade-off between speed, power, and  noise of op amp regardless of its gain. Digitally correct for everything!  Slides by Bibhudatta Sahoo -42- 42

How to Calibrate?  Inverse Operator estimation can be done in:  Background  Foreground Slides by Bibhudatta Sahoo -43- 43

Capacitor Mismatch Calibration Slides by Bibhudatta Sahoo -44- 44

Comparator Forcing Based Calibration where, and B. Sahoo and B. Razavi, IEEE JSSC , vol. 48, pp. 1442-1452, Jan. 2013. Slides by Bibhudatta Sahoo -45- 45

Computation of 𝛾 𝑘 (I) In other words, Slides by Bibhudatta Sahoo -46- 46

Computation of 𝛾 𝑘 (II) In other words, ’s can be calculated using adders and right shifts. B. Sahoo and B. Razavi , “A 10 -b 1-GHz 33- mW CMOS ADC“, IEEE Journal of Solid - State Circuits, vol. 48, pp. 1442-1452, Jun. 2013. A. Karanicolas , et. al., “A 15 -b 1-Msample/s digitally self-calibrated pipeline ADC, “, IEEE Journal of Solid -State Circuits, vol. 28, pp. 1207-1215, Dec. 1993. Slides by Bibhudatta Sahoo -47- 47

Capacitor Mismatch Calibration (1)  The input output characteristic of a 4-bit stage is: 16 15    C V C A V m IN m m , j R    m 1 m 1 V OUT 16    C C C F P m   m 1 C F A 9 15  C A V m m , j R      1 m V V OUT IN 16    C C C F P m   m 1 C F A      V V V , OUT IN j R 15 16   C A V C m m , j R m       m 1 i 1 where and . j 16 16  Dividing both sides by V R we get,       C C C C C C     F P m F P m  D BE =backend digital output D D     m 1 m 1 BE IN j C C F F A A  D    j BE D   IN Slides by Bibhudatta Sahoo -48-

Capacitor Mismatch Calibration (2)       · · ·     · · ·  C C C C C C C               1 2 14 15 1 2 15 Region 15 : D D D Region 1 : D D D BE IN IN 15 BE IN IN 1 16 16       C C C C C C F P i F P i     i 1 C i 1 C F F A A         · · ·    · · ·  C C C C C C               1 2 15 Region 16 : D D D 1 2 15 Region 2 : D D D BE IN IN 16 16  BE IN IN 2 16      C C C C C C F P i F P i   i 1 C   i 1 C F A F A        · · ·  C C C C        1 2 3 15 Region 3 : D D D BE IN IN 3 16    C C C F P i   i 1 C F A Slides by Bibhudatta Sahoo -49-

Capacitor Mismatch Calibration (3)  The digital output goes from 0 to 15 when the input changes from – V R to +V R .  Apply V j close to the comparator threshold and force the flash ADC output so that the residue is once in region j and then in region (j+1).  The redundancy/offset correction range in the architecture prevents the ADC from clipping.  The backend ADC gives two different codes for the same input voltage. Slides by Bibhudatta Sahoo -50-

Capacitor Mismatch Calibration (4)   Applying V j to the ADC in region j we get, D   BE , j j D   j  Similarly applying V j and forcing the flash ADC output to be in region (j+1) we get,  D    BE , j , f j 1 D   j , f  Since, same voltage is applied we can equate both of them:      D D  BE , j , f BE , j j j 1 which is not dependent on gain error.  Repeat the above steps for j=1 to 15 . Slides by Bibhudatta Sahoo -51-

Capacitor Mismatch Calibration (5)  Thus we end up with:       D D         D D 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BE , 1 , f BE , 1 1 2 BE , 1 , f BE , 1 1               D D D D 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0       BE , 2 , f BE , 2 2 3 BE , 2 , f BE , 2 2               D D D D 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 BE , 3 , f BE , 3 3 4 BE , 3 , f BE , 3 3               D D 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0  D D      BE , 4 , f BE , 4 4 5 BE , 4 , f BE , 4 4               D D D D 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 BE , 5 , f BE , 5 5 6       5 BE , 5 , f BE , 5           D D     D D 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 BE , 6 , f BE , 6 6 7 BE , 6 , f BE , 6 6               D D D D 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0       BE , 7 , f BE , 7 7 8 BE , 7 , f BE , 7 7                D D 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 D D BE , 8 , f BE , 8 8 9 BE , 8 , f BE , 8 8               D D D D 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0       BE , 9 , f BE , 9 9 10 9 BE , 9 , f BE , 9               D D D D 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 , 10 , , 10 10 11 BE , 10 , f BE , 10 BE f BE 10               D D 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0   D D     BE , 11 , f BE , 11 BE , 11 , f BE , 11 11 12 11               D D 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 D D  BE , 12 , f BE , 12     12  BE , 12 , f BE , 12 12 13               D D 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 D D , 13 , , 13 13 BE f BE , 13 , , 13 13 14 BE f BE               D D 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D D       BE , 14 , f BE , 14 14 BE , 14 , f BE , 14 14 15                  D D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1   D D BE , 15 , f BE , 15 15 BE , 15 , f BE , 15 15 1  Solving for  j is straight forward and does not require multiplication. Slides by Bibhudatta Sahoo -52-

Capacitor Mismatch Calibration (6)  Thus  j can be obtained as follows without the need of multipliers:         D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BE , 1 , f BE , 1 1          1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D D       BE , 2 , f BE , 2 2           D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BE , 3 , f BE , 3 3            D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       , 4 , , 4 4 BE f BE             1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D D       BE , 5 , f BE , 5 5              D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BE , 6 , f BE , 6 6               D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       7 BE , 7 , f BE , 7 1                 D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BE , 8 , f BE , 8 8     2             D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       BE , 9 , f BE , 9 9                  D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 BE , 10 , f BE , 10                   D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       BE , 11 , f BE , 11 11                    D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1  BE , 12 , f BE , 12   12                   D D     1 1 1 1 1 1 1 1 1 1 1 1 1 1 1  13 BE , 13 , f BE , 13                      D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       BE , 14 , f BE , 14 14                           D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1   BE , 15 , f BE , 15 15  Combining the bits with appropriate  j :  Flash ADC output tells us which region the analog voltage is in.  The above information can be used appropriately combine the bits. Slides by Bibhudatta Sahoo -53-

Gain Calibration for Multi-bit MDAC Slides by Bibhudatta Sahoo -54- 54

Computation of  Need to obtain C 1 /C eq , C 2 /C eq ,…, C 16 /C eq .  Fortunately,  We already have these values from previous measurements  Slides by Bibhudatta Sahoo -55- 55

Computation of C 16 /C eq Swap C 1 and  C 16 :    Thus, is obtained.  Slides by Bibhudatta Sahoo -56- 56

Gain Error Calibration (1)     · · ·  C C C  We can obtain a similar set of        16 2 15 Region 1 : D D D BE IN IN 1 16  measurements by connecting C 16 to   C C C F P i  V R (controlled by A 1 ) and C 1 to   i 1 C F A V CM .       · · ·  C C C         Instead of  1 to  15 we can define 16 2 15 Region 2 : D D D BE IN IN 2 16     1 to  15 as shown on the side. C C C F P i   i 1 C  Similarly we can solve for  1 to F A      15 by matrix inversion.    · · ·  C C C C        16 2 3 15 Region 3 : D D D BE IN IN 3 16    C C C F P i   i 1 C F A · · ·      · · ·  C C C C        16 2 3 15 Region 15 : D D D BE IN IN 15 16    C C C F P i   i 1 C F A      · · ·  C C C C        16 2 3 15 Region 16 : D D D BE IN IN 1 16    C C C F P i   i 1 C F A Slides by Bibhudatta Sahoo -57-

Gain Error Calibration (2)  We can rewrite  1 to  15 in terms C 1 to C 16 as shown below:                       1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C 1 1                      C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       2 2                     1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C 3 3                     1 1 1 1 1 1 1 1 1 1 1 1 1 1 1   C    4 4                   1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C       5 5                  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C 6 6                 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C       7 7 1                 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C   8 8 16                    C C C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C       F P i 9 9     i 1              C   1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C F A 10 10               1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C         11 11            1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C       12 12      1 1 1 1 1 1 1 1 1 1 1 1 1 1 1   C    13 13          1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C       14 14          1 1 1 1 1 1 1 1 1 1 1 1 1 1 1   C    15 15  Similarly, we can rewrite  1 to  15 in terms C 2 to C 16 . 16    C C C F P i  Solving the two matrices we can obtain C i /(C F -C X ) where,   i 1 C X A for i=1 to 16. 16 C   Gain error,   i  C C  i 1 F X Slides by Bibhudatta Sahoo -58-

Gain Error Calibration – 1.5 bit stages  Backend stages  need gain error calibration.  Perturbation based calibration [1]:  Applying V IN we get D 0 and D BE0 .  Applying (V IN +  ) we get D 1 and D BE1 .  Applying  we get D 0 and D BE  .  V IN and (V IN +  ) should produce different codes.  Thus, gain error  is obtained as follows:         V V 0 IN IN           D D D D D D 0  1 BE 1 0 BE 0 0 BE D    1   D D D  BE 0 BE BE 1 [1] B. Sahoo and B. Razavi, "A 12-Bit 200- MHz CMOS ADC,“ IEEE Journal of Solid- State Circuits, vol. 44, pp. 2366-2380, Sept. 2009 Slides by Bibhudatta Sahoo -59-

Gain Calibration for 1.5-bit Non-flip-around MDAC Slides by Bibhudatta Sahoo -60- 60

1.5-Bit Stages where, is the gain.  C S and C F cannot be swapped to obtain gain as it would lead to over-range. Slides by Bibhudatta Sahoo -61- 61

Calibration Algorithm* (1.5-Bit Stages) • Apply  V  10 mV • Apply V REF /4 • Apply V REF /4+  V * B. Sahoo and B. Razavi, IEEE Journal of Solid-State Circuits , vol. 44, pp. 2366-2380, Sept. 2009 Slides by Bibhudatta Sahoo -62- 62

1.5-Bit Stages - Computing Inverse Gain (1/  ) • Apply  V • Apply V REF /4, force comparator output to be “0” • Apply (V REF /4+  V), force comparator output to be “1” Inverse Gain = • Obtained using Newton-Raphson iterative method instead of division. Slides by Bibhudatta Sahoo -63- 63

Gain Calibration for 1.5-bit Flip-around, 2.5-bit, etc. MDAC Slides by Bibhudatta Sahoo -64- 64

Gain Calibration for 1.5-bit Flip-around MDAC (1) 𝑫 𝟐 +𝑫 𝟑 𝑫 𝟐 𝑾 𝒑𝒗𝒖 = 𝑾 𝒋𝒐 − 𝑳𝑾 𝑺 , where 𝑳 = ±𝟐, 𝟏 𝑫 𝟑 + 𝑫𝟐+𝑫𝟑+𝑫𝑸 𝑫 𝟑 + 𝑫𝟐+𝑫𝟑+𝑫𝑸 𝑩 𝑩 𝑫 𝟐 +𝑫 𝟑 𝑫 𝟐 ⟹ 𝑾 𝒑𝒗𝒖 = 𝜷𝑾 𝒋𝒐 − 𝑳𝜸𝑾 𝑺 , where 𝜷 = , and 𝜸 = 𝑫 𝟑 + 𝑫𝟐+𝑫𝟑+𝑫𝑸 𝑫 𝟑 + 𝑫𝟐+𝑫𝟑+𝑫𝑸 𝑩 𝑩 𝜸 can be solved by applying 𝑾 𝑼𝟐 or 𝑾 𝑼𝟑 and forcing the corresponding  comparator to “1” or “0”. Unlike, an N-bit architecture as mentioned earlier we cannot swap the  capacitors here to solve for 𝜷 . 𝑫 𝟐 +𝑫 𝟑 +𝑫 𝑸 𝑫 𝟐 +𝑫 𝟑 +𝑫 𝑸 Swapping capacitors changes the denominator 𝑫 𝟑 + to 𝑫 𝟐 +  𝑩 𝑩 * C. Ravi, V. Sarma , and B. Sahoo,“ IEEE NEWCAS, June 2015 Slides by Bibhudatta Sahoo -65- 65

Gain Calibration for 1.5-bit Flip-around MDAC (2) 𝑫 𝟐 +𝑫 𝟑 𝑫 𝟐 𝑾 𝒑𝒗𝒖 = 𝑾 𝒋𝒐 − 𝑳𝑾 𝑺 , where 𝑳 = ±𝟐, 𝟏 𝑫 𝟑 + 𝑫𝟐+𝑫𝟑+𝑫𝑸 𝑫 𝟑 + 𝑫𝟐+𝑫𝟑+𝑫𝑸 𝑩 𝑩 𝑫 𝟐 +𝑫 𝟑 𝑫 𝟐 ⟹ 𝑾 𝒑𝒗𝒖 = 𝜷𝑾 𝒋𝒐 − 𝑳𝜸𝑾 𝑺 , where 𝜷 = , and 𝜸 = 𝑫 𝟑 + 𝑫𝟐+𝑫𝟑+𝑫𝑸 𝑫 𝟑 + 𝑫𝟐+𝑫𝟑+𝑫𝑸 𝑩 𝑩 Applying 𝑾 𝑺 the back-end ADC output can be given as:  𝑫 𝟑 𝑫 𝟑 𝑾 𝒑𝒗𝒖 = 𝜷𝑾 𝑺 − 𝜸𝑾 𝑺 ⟹ 𝑾 𝒑𝒗𝒖 = 𝑾 𝑺 ⟹ 𝑬 𝑪𝑭 = 𝑫 𝟑 + 𝑫 𝟐 + 𝑫 𝟑 + 𝑫 𝑸 𝑫 𝟑 + 𝑫 𝟐 + 𝑫 𝟑 + 𝑫 𝑸 𝑩 𝑩 The 𝜸 obtained using the comparator forcing algorithm can be added to the  above 𝑬 𝑪𝑭 measurement to obtain 𝜷 * C. Ravi, V. Sarma , and B. Sahoo,“ IEEE NEWCAS, June 2015 Slides by Bibhudatta Sahoo -66- 66

Gain Calibration for 2.5-bit Flip-around MDAC Comparator forcing based  calibration technique is used to obtain 𝜸 𝟐 to 𝜸 𝟕 . Just as in 1.5-bit flip-around  topology swapping capacitor changes the denominator and hence cannot be used to solve for the gain 𝜷 . Applying the full-scale input  to the MDAC and digitizing the output using the backend we obtain, 𝑫 𝟖 + 𝑫 𝟗 𝑬 𝑪𝑭 = 𝟗 𝑫 𝟖 + 𝑫 𝟗 + 𝒋=𝟐 𝑫 𝒋 + 𝑫 𝑸 𝟗 𝟕 𝒋=𝟐 𝒋=𝟐 𝑫 𝒋 𝑾 𝒋𝒐 𝑼 𝒋 𝑫 𝒋 𝑾 𝒑𝒗𝒖 = − 𝑾 𝑺 𝑩 𝟗 𝟗 𝑫 𝟖 + 𝑫 𝟗 + 𝒋=𝟐 𝑫 𝟖 + 𝑫 𝟗 + 𝒋=𝟐 𝑫 𝒋 + 𝑫 𝑸 𝑫 𝒋 + 𝑫 𝑸 𝟕 𝒋=𝟐 𝑫 𝒋 Now, 𝜸 𝟕 = . 𝑩 𝑩  𝟗 𝒋=𝟐 𝑫𝒋+𝑫𝑸 ⟹ 𝑾 𝒑𝒗𝒖 = 𝜷𝑾 𝒋𝒐 − 𝜸 𝒋 𝑾 𝑺 𝑫 𝟖 +𝑫 𝟗 + 𝑩 𝜷 = 𝑬 𝑪𝑭 + 𝜸 𝟕  Can be extended to 3.5-bit.  * C. Ravi, V. Sarma , and B. Sahoo,“ IEEE NEWCAS, June 2015 Slides by Bibhudatta Sahoo -67- 67

Calibration at Full-Speed Speed of existing calibration methods are limited by   Circuitry which applies the calibration inputs Calibration at low speed doesn't capture the error in  residue  Due to insufficient settling of the op amp at high frequency  Incorrect gain estimation In order to facilitate calibration at full-speed the  calibration voltages have to be generated using capacitors switching to ±𝑾 𝑺 . This eliminates the resistor ladder to generate the  calibration voltages. * C. Ravi, V. Sarma , and B. Sahoo,“ IEEE NEWCAS, June 2015 Slides by Bibhudatta Sahoo -68- 68

Calibration Signal Generation for 1.5-bit Stage (1) Split the sampling capacitor and  the feedback capacitor into two equal unit capacitors During normal operation   Sampling phase: Input is sampled onto all the capacitors  Amplification phase: 2 capacitors are flipped around  Remaining two capacitors switch to 𝑳𝑾 𝑺 * C. Ravi, V. Sarma , and B. Sahoo,“ IEEE NEWCAS, June 2015 Slides by Bibhudatta Sahoo -69- 69

Calibration Signal Generation for 1.5-bit Stage (2) During Calibration,  Sampling phase: −𝑾𝑺 sampled  onto one sampling capacitors  Remaining capacitors connected to ground for applying 𝑾 𝑼𝟐 = −𝑾𝑺/𝟓 .  Amplification phase: Two capacitors connected to 𝑳𝑾 𝑺  Two capacitors flipped around Resulting residue voltage is  −𝑾 𝑺 𝑫 𝟐 + 𝑳𝑾 𝑺 𝑫 𝟐 + 𝑫 𝟑 𝑾 𝒑𝒗𝒖 = 𝑫 𝟒 + 𝑫 𝟓 + 𝑫 𝟐 + 𝑫 𝟑 + 𝑫 𝟒 + 𝑫 𝟓 𝑩 This residue is same as if 𝑾 𝑱𝑶 =  −𝑾𝑺/𝟓 is applied * C. Ravi, V. Sarma , and B. Sahoo,“ IEEE NEWCAS, June 2015 Slides by Bibhudatta Sahoo -70- 70

Calibration Signal Generation for 1.5-bit Stage (3) Similarly, we can mimic the generation  of 𝑾 𝑼𝟑 = 𝑾𝑺/𝟓 by Applying 𝑾 𝑺 to one sampling  capacitor  Remaining connected to ground * C. Ravi, V. Sarma , and B. Sahoo,“ IEEE NEWCAS, June 2015 Slides by Bibhudatta Sahoo -71- 71

Background Gain Calibration for Multi-bit, 1.5-bit, 2.5-bit, etc. MDACs Slides by Bibhudatta Sahoo -72- 72

Pipeline Stage I/O Characteristic  The input output characteristic of a 4-bit stage is: 16 15    C V C A V m IN m m , j R    m 1 m 1 V OUT 16    C C C F P m   m 1 C F A 9 15  C A V m m , j R      m 1 V V OUT IN 16    C C C F P m   m 1 C F A      V V V , OUT IN j R 15 16   C A V C m m , j R m       m 1 i 1 where and . j 16 16        Dividing both sides by V R we get, C C C C C C F P m F P m     m 1 m 1 C C F F A A     D D BE IN j D     BE D IN  j where,  j is the capacitor mismatch  independent of op amp gain   is the gain ( G 1 )  function of op amp gain.  Slides by Bibhudatta Sahoo -73- 73

Proposed Calibration Algorithm Initially estimate the gain (  =G 1 ) and the capacitor  mismatch (  j ) in the foreground using the calibration technique in  . Then estimate the inter-stage gain α , in the background.  9  B. Sahoo, and B. Razavi , ”A 10 -bit 1-GHz 33- mW CMOS ADC,” IEEE JSSC , June 2013. Slides by Bibhudatta Sahoo -74- 74

Pipelined Stage Residue Characteristic with MDAC Gain Variation 2-bit MDAC residue characteristics 2-bit MDAC residue characteristics V res Vs V in with Gain variation D BE Vs V in with Gain variation MDAC gain ( 𝜷 ) changes  slope of the residue characteristic changes.  Residue quantized by an ideal 𝑵 -bit back-end to give a digital estimate,  𝑬 𝑪𝑭 , 𝑬 𝑪𝑭, min = 2 M-2 and 𝑬 𝑪𝑭, max = 3 ´ 2 M-2 -1 Ideally  = 𝑬 𝑪𝑭, max /𝑾𝑴𝑻𝑪/𝟑 .  Parameter drift changes 𝑬 𝑪𝑭, min and 𝑬 𝑪𝑭, max .  Slides by Bibhudatta Sahoo -75- 75

Calibration Algorithm Estimate the MDAC gain, α in the foreground mode using  technique in  . Estimate D BE,max1 in the background mode, immediately after the  foreground calibration is done. Thus,  = D BE,max1 / V LSB /2. Calibration engine keeps on estimating D BE,max . If the gain drifts a  new back-end maximum, D BE,max2 is obtained, resulting in  new = D BE,max2 / V LSB /2. Thus,  new      D D max 2 max 2  new D D max 1 max 1  B. Sahoo, and B. Razavi , “A 10 -bit 1-GHz 33- mW CMOS ADC,” IEEE JSSC , June 2013. Slides by Bibhudatta Sahoo -76- 76

Effect of Non-Idealities The estimation of 𝑬 𝑪𝑭, 𝑵𝑩𝒀 can be corrupted due  to the following non-idealities:  Comparator Offset  Capacitor mismatch  Thermal Noise Slides by Bibhudatta Sahoo -77- 77

Effect of Comparator Offset With comparator offset maximum back-  end code changes from region to region, but slope in each region is the same. Maximum in any one region gives the  accurate estimate of inter-stage gain The region should be such that the  calibration can work even with lower signal swing For 2-bit MDAC, characteristic  corresponding to output code of 1 or 2 is chosen For 3-bit and 4-bit MDACs calibration would work for 1/4 th and  1/8 th of the signal swing. Proposed calibration would thus require a minimum swing that is either 12 dB or 18 dB below full scale. Slides by Bibhudatta Sahoo -78- 78

Effect of Capacitor Mismatch Capacitor mismatch changes the  residue/back-end characteristic. Although the slope is the same in  each region the maximum in each region is different. Calibration obtains the maximum  back-end code for a particular region Slides by Bibhudatta Sahoo -79- 79

Effect of Thermal Noise Thermal noise corrupts the measurement  of D BE,max . Histogram of the back-end code estimates  the true maximum code and eliminates the absolute maximum code. For a noisy bin to have the same height as that of a noiseless bin,  the thermal noise should have a variance, σ NTH > 10 LSB  SNR degradation of approx. 30 dB.  Noisy bins cannot be of the same height as noiseless bins Slides by Bibhudatta Sahoo -80- 80

Multi-stage Gain Calibration Algorithm first calibrates the 2 nd stage that has an ideal back-  end Consider the 2 nd stage onwards as an ideal back-end and  calibrate the 1 st stage Calibration starts from the later stages and moves to the 1 st  stage Slides by Bibhudatta Sahoo -81- 81

Digital Hardware Complexity Histogram requires counters and finding the maximum requires  comparators. No  For M-bit back-end, do we need 2 M comparators and counters!  Foreground calibration gives an initial estimate of D BE,max and noise  corrupts this by maximum of ± 10 to ± 20 back-end codes Hence maximum of 40 digital comparators and counters used  Division operation is realized using Newton-Raphson technique,  which requires a multiplier and adder Slides by Bibhudatta Sahoo -82- 82

Survey of Digital Calibration Techniques Slides by Bibhudatta Sahoo -83- 83

Survey of Calibration Techniques Sl. Author Type of Foreground/ Notes No. (Year) MDAC Background 1. Lee Multi-bit Foreground Capacitor mismatch and gain error (1992) 2. Karanicolas 1-bit Foreground Gain error (1992) 3. Erdogan 1-bit Background Gain error (1999) 4. Ming 1.5-bit non- Background Gain error (2001) flip around 5. Li (2003) 1.5-bit flip- Background Gain error around 6. Murmann 3-bit Background Capacitor mismatch, op amp (2003) nonlinearity, and gain error 7. Wang 1.5-bit flip- Background Gain error and capacitor mismatch. (2004) around 8. Verma 1.5-bit flip- Foreground Gain error, op amp nonlinearity, (2009) around and capacitor mismatch Slides by Bibhudatta Sahoo -84- 84

Calibration of Multistep ADC (1) S-H. Lee and B-S. Song, IEEE JSSC , vol. 27, pp. 1679-1688, Dec. 1992. Slides by Bibhudatta Sahoo -85- 85

Calibration of Multistep ADC (2)  Error ( 𝑬 𝒌 ) and Error ( 𝑬 𝒌 + 𝟐 ) are the errors with digital codes 𝑬 𝒌 and 𝑬 𝒌 + 𝟐 . S-H. Lee and B-S. Song, IEEE JSSC , vol. 27, pp. 1679-1688, Dec. 1992. Slides by Bibhudatta Sahoo -86- 86

Calibration of Multistep ADC (3)  Measure the feedthrough voltage, i.e. offset, charge-injection, etc.  Change the digital code by “1” and measure the output voltage.  When digital code is changed by “1” then the change in the output should be exactly ½ 𝑾 𝑺𝑭𝑮 .  Thus the Error ( D j+1 ) can be obtained from the above measurement and stored in memory. S-H. Lee and B-S. Song, IEEE JSSC , vol. 27, pp. 1679-1688, Dec. 1992. Slides by Bibhudatta Sahoo -87- 87

15-bit Self Calibrated Pipelined ADC (1) 𝑾 𝒑𝒗𝒖 = 𝟑 + 𝜷 𝟐 + 𝜷 𝑾 𝒋𝒐 − 𝑬𝑾 𝒔𝒇𝒈 where, 𝑫 𝟑 = 𝟐 + 𝜷 𝑫 𝟐  Capacitor mismatch is merged with the gain term. A. Karanicolas and H. S. Lee, IEEE JSSC , vol. 28, pp. 1207-1215, Dec. 1993. Slides by Bibhudatta Sahoo -88- 88

15-bit Self Calibrated Pipelined ADC (2)  Measure two quantities S 1 and S 2 by applying V in in =0 =0 and forcing D =0 =0 and D =1 =1 .  Thus, the output can be given by, 𝒁 = 𝒀 if 𝑬 = 𝟏 = 𝒀 + 𝑻 𝟐 − 𝑻 𝟑 if 𝑬 = 𝟐 .  Calibration estimates only 𝑻 𝟐 and 𝑻 𝟑 for each stage, stores them and then uses them in the digital calibration logic.  Calibration does not require multiplication.  Calibration starts from the later stages and moves to the earlier stages.  Difficult for a multi-bit stage. A. Karanicolas and H. S. Lee, IEEE JSSC , vol. 28, pp. 1207-1215, Dec. 1993. Slides by Bibhudatta Sahoo -89- 89

Queue Based Algorithmic ADC Calibration (1)  Queue based background gain error calibration.  Having “ n ” sample -and-hold (SHA) and choosing f c > f s , time slots for calibrating the ADC can be obtained without compromising the normal operation of the ADC.  The number of SHAs is given by: 𝒐 ≥ 𝑼 𝒅𝒃𝒎 𝑼 𝑻 where, T cal is the calibration time and T s = 1 /f s .  Each of the SHA adds noise and degrades the SNR of the ADC.  Also the additional SHA’s consume significant power.  The paper demonstrates this for a Algorithmic ADC.  It can also be extended to a pipelined ADC. O. E. Erdogan, P . J. Hurst, and S. H. Lewis, IEEE JSSC , vol. 34, pp. 1812-1820, Dec. 1999. Slides by Bibhudatta Sahoo -90- 90

Queue Based Algorithmic ADC Calibration (2) O. E. Erdogan, P . J. Hurst, and S. H. Lewis, IEEE JSSC , vol. 34, pp. 1812-1820, Dec. 1999. Slides by Bibhudatta Sahoo -91- 91

Queue Based Algorithmic ADC Calibration (3)  After the queue is empty the ADC goes into calibration mode.  The ADC uses a 1-bit architecture just like in Karanicolas 1993.  The nominal gain “ m < 2” to make sure that there are no missing levels.  Since the actual value of “ 𝒏 ” is not known an initial estimate of “ 𝒏 ” is used to obtain the digital output: 𝑶 𝒏 𝒋 𝒆 𝒋 𝑬 = 𝒋=𝟐  During calibration an input of 0 V is applied and the comparator output is forced to “1” and “0” to obtain respectively D 1 and D 0 .  LMS is used to estimate “ 𝒏 ” as per the following: 𝒏 𝒌 + 𝟐 = 𝒏 𝒌 + 𝝂 𝑬 𝟐 − 𝑬 𝟏 − 𝟐𝑴𝑻𝑪 O. E. Erdogan, P . J. Hurst, and S. H. Lewis, IEEE JSSC , vol. 34, pp. 1812-1820, Dec. 1999. Slides by Bibhudatta Sahoo -92- 92

8-bit Pipelined ADC With Background Calibration (1) 1.5-bit MDAC architecture 𝑾 𝒑𝒗𝒖 = 𝑫 𝑻 𝟐 𝑾 𝒋𝒐 − 𝒍𝑾 𝑺𝑭𝑮 𝟐 + 𝟐 𝑩 + 𝑫 𝑻 + 𝑫 𝒀 𝑫 𝑮 𝑩𝑫 𝑮  𝑾 𝒑𝒗𝒖 = 𝑯 𝑱 𝑯 𝑭 𝑾 𝒋𝒐 − 𝒍𝑾 𝑺𝑭𝑮 𝑫 𝑻 𝟐 where, 𝑯 𝑱 = 𝑫 𝑮 and 𝑯 𝑭 = 𝑩 + 𝑫𝑻+𝑫𝒀 𝟐+ 𝟐 𝑩𝑫𝑮 𝑾 𝑺𝟑 Adjust 𝑾 𝑺𝟐 = 𝑯 𝑭 to overcome the gain-error. J. Ming and S. H. Lewis, IEEE JSSC , vol. 36, pp. 1489-1497, Oct. 2001. Slides by Bibhudatta Sahoo -93- 93

8-bit Pipelined ADC With Background Calibration (2)  A pseudo-random generator generates a  1 digital number.  The random number is converted to analog by DAC 1 .  The output of DAC 1 is digitized by the back-end ADC and by a slow-but- accurate ADC.  The slow-but-accurate ADC output should be subtracted from the back- end ADC output to recover the digital representation of Vin.  The gain error of the stage can be obtained if e i does not contain the random input N ( i ) . This is possible if: 𝑾 𝒐 𝑯 𝑬𝟐 − 𝑾 𝒐 = 𝟏 → 𝑾 𝑺𝟐 = 𝑾 𝑺𝟑 𝑾 𝑺𝟑 𝑾 𝑺𝟐 𝑯 𝑬𝟐 J. Ming and S. H. Lewis, IEEE JSSC , vol. Slides by Bibhudatta Sahoo -94- 94 36, pp. 1489-1497, Oct. 2001.

8-bit Pipelined ADC With Background Calibration (3)  Needs extensive analog hardware for calibration.  The DAC in the calibration system should be accurate  difficult to calibrate high resolution ADCs (> 10- bits).  Calibration technique can effectively calibrate 1.5-bit/stage architecture and not multi-bit architecture.  Extension to multi-bit architecture is very hardware intensive. Multi-stage calibration J. Ming and S. H. Lewis, IEEE JSSC , vol. 36, pp. 1489-1497, Oct. 2001. Slides by Bibhudatta Sahoo -95- 95

Radix Based Calibration (1) 𝟐 𝑫 𝑻 + 𝑫 𝑮 𝑾 𝒋 − 𝑫 𝑻 𝑾 𝑷 = 𝑬𝑾 𝒔𝒇𝒈 𝟐 + 𝑫 𝑻 + 𝑫 𝑮 𝑫 𝑮 𝑫 𝑮 𝑾 𝑷 = 𝟑𝑫 𝑻 𝟐 𝑾 𝒋 − 𝟐 𝑩𝑫 𝑮 𝟑 𝑬𝑾 𝒔𝒇𝒈 𝟐 + 𝟑𝑫 𝑻 + 𝑫 𝑮 𝑫 𝑮 𝑾 𝒋 − 𝟐 + 𝜸 𝑩𝑫 𝑮 → 𝑾 𝑷 = 𝟐 + 𝜺 𝟑 + 𝜷 𝟑 + 𝜷 𝑬𝑾 𝒔𝒇𝒈 → 𝑾 𝑷 = 𝟐 + 𝜺 𝟑 + 𝜷 𝑾 𝒋 − 𝑬𝑾 𝒔𝒇𝒈 𝟐 , 𝟑 + 𝜷 = 𝑫 𝑻 +𝑫 𝑮 where, 𝟐 + 𝜺 = 𝑫 𝑮 , 𝟐 𝐛𝐨𝐞 𝟑 + 𝜷 = 𝑫 𝑻 +𝑫 𝑮 𝟐+ 𝑫𝑻+𝑫𝑮 where, 𝟐 + 𝜺 = 𝑫 𝑮 , 𝟐+ 𝑫𝑻+𝑫𝑮 𝑩𝑫𝑮 𝑩 and 𝟐 + 𝜸 = 𝑫 𝑻 𝑫 𝑮 J. Li and Un-Ku Moon, IEEE TCAS-I , vol. 50, pp. 531-538, Sept. 2003. Slides by Bibhudatta Sahoo -96- 96

Radix Based Calibration (2) Representation of the pipelined ADC with each stage using 1.5-bit non-flip around topology.  The digital output can be represented as: 𝑬 𝑷 = 𝑬 𝒐 + 𝑬 𝒐 𝒔𝒃 + 𝑬 𝒐 𝒔𝒃 𝟑 + ⋯ + 𝑬 𝟐 𝒔𝒃 𝒐−𝟐 where, 𝒔𝒃 = 𝟐 + 𝜺 𝟑 + 𝜷 and reference voltage of each stage is scaled.  Since the reference is scaled for each stage this is not attractive.  However if each stage uses a non-flip-around topology then, 𝑬 𝑷 = 𝑬 𝒐 + 𝑬 𝒐 𝒔𝒃 + 𝑬 𝒐 𝒔𝒃 𝟑 + ⋯ + 𝑬 𝟐 𝒔𝒃 𝒐−𝟐 where, 𝒔𝒃 = 𝟐 + 𝜺 𝟑 + 𝜷 and reference voltage of each stage is not scaled. J. Li and Un-Ku Moon, IEEE TCAS-I , vol. 50, pp. 531-538, Sept. 2003. Slides by Bibhudatta Sahoo -97- 97

Radix Based Calibration (3) 𝟑+𝜷 𝒋+𝟐  The new radix is . 𝒔𝒃 = 𝟐 + 𝜸 𝒋 𝟐 + 𝜺 𝒋 𝟐+𝜸 𝒋+𝟐 .  The reference voltage is not scaled from stage-to-stage. J. Li and Un-Ku Moon, IEEE TCAS-I , vol. 50, pp. 531-538, Sept. 2003. Slides by Bibhudatta Sahoo -98- 98

Radix Based Calibration (4)   J. Li and Un-Ku Moon, IEEE TCAS-I , vol. 50, pp. 531-538, Sept. 2003. Slides by Bibhudatta Sahoo -99- 99

Radix Based Calibration (5) · Large convergence time as D BE has to be correlated for a long time to guarantee that P N  D res vanishes. · Generation of precise analog voltage  V PN whose digital value is PN. · Reduction in dynamic range of the ADC due to injection of pseudorandom voltage  V PN . J. Li and Un-Ku Moon, IEEE TCAS-I , vol. 50, pp. 531-538, Sept. 2003. Slides by Bibhudatta Sahoo -100- 100