A Routing Approach to Reduce Glitches in Low Power FPGAs Quang - - PowerPoint PPT Presentation

A Routing Approach to Reduce Glitches in Low Power FPGAs

Quang Dinh, Deming Chen, Martin Wong

Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign

This research was supported by Altera and NSF

Outline

Introduction Background Routing Approach Path-Finding Algorithm Results

Dynamic Power

67% of total power

(Stratix II FPGAs)

Glitch

Up to 60% of total

dynamic power

Glitch Reduction

Lower Dynamic Power

Dynamic Power and Glitch

Related Works

High-Level

Logic decomposition [Monteiro et al., 1998] RTL synthesis [Raghunathan et al., 1999]

Not applicable to FPGA

Gate freezing [Benini et al., 2000] Delay insertion [Raghunathan et al., 1999]

FPGA specific

GlitchMap [Cheng et al., 2007] GlitchLess [Jamoureux et al., 2007]

FPGA Interconnect

Island-Style FPGA Interconnect delay is more

significant than logic delay

Programmable interconnects

with fixed delays

Rich, under-used interconnect

resource

[Betz et al., 1999]

Routing Approach

Reduce Glitches by balancing input arrival times

By routing through paths with desired delays Lengthen paths of early-arriving inputs

No Architectural Modification

Applied to existing FPGAs

Do not affect critical path delay

FPGA Routing Architecture

Routing resource graph Assumption: Buffered Switches

True for commercial FPGAs (boost performance) Linear delay model for paths

[Betz et al., 1999]

Algorithm Overview

Get an valid routing solution (VPR router) Reduce Glitches by Balancing certain source-

sink pairs

Selection and Ordering of pairs Rip-up and re-route each pair Reroute with Path-Finding Algorithm

Find path with desired delay

Selection Criteria

Power overhead due to

longer path

More capacitance, more

buffers

Balance only beneficial

inputs

Heuristic: Balancing inputs

• f 1st-level clusters

0.2 0.4 0.6 0.8 1 1.2 1st Level 2nd Level All Switching Reduction Capacitance Increase

Ordering Criteria

LUT Input Weighting

Likelihood of glitch generation Signal probability of Boolean difference

Balancing overhead

Prefer small increase delays over large increase

Path ranking

Inputs:

Routing-resource graph (V, E) with delay information Source-sink pair (s, t) Desired delay range d±Δ

Output:

Path from s to t with desired delay Not always has a solution

Path-Finding Algorithm

s t

Motivation

Try every paths: exponential complexity Heuristic: Select a manageable subset of paths

Polynomial complexity Still provide reasonable quality of results Wide range of path lengths

Motivation

Efficient path algorithm:

shortest path

Find only path with

smallest delay

Detour

Combine shortest paths Increase path delay

s t d

Motivation

Efficient path algorithm:

shortest path

Find only path with

smallest delay

Detour

Combine shortest paths Increase path delay

Problem: overlapping

s t d

Candidate Paths

s t Set S Set T s t'

Set S: vertices closer to s Set T: vertices closer to t (s’, t’): direct connection (edge) Guarantee no overlapping

Glitch-Reducing Framework

Run timing-driven VPR router to get a routing solution for each 1-st level CLB input get desired balanced delay compute path rank end Sort these inputs by their rank for each input rip-up current path use path-finding algorithm to find a path with the desired delay if can not find such a path restore the ripped-up path end end

Experiment Settings

20 largest circuits from MCNC and ISCAS89 Timing-driven place and route by VPR 4-LUT, cluster size 4 Power simulator fpgaEVA-LP2 [Li et al., 2005]

Dynamic power Glitch power Switching activity

Results

49.0 36.9 9.85 average 0.8 0.7 3.33 3.42 3.49 C880 17.9 9.1 11.40 38.55 43.51 C7552 6.1 4.9 18.84 59.39 73.20 C6288 14.0 7.2 8.82 31.03 34.08 C5315 0.8 0.6 13.78 3.07 3.59 C499 0.6 0.4 7.81 2.44 2.68 C432 3.8 3.5 11.45 19.05 21.54 C3540 8.3 4.0 5.24 11.87 12.64 C2670 1.5 1.0 8.94 7.13 7.82 C1908 1.1 0.6 12.04 3.24 3.71 C1355 148.1 139.2 8.76 31.09 33.80 spla 41.1 28.6 5.42 32.92 34.92 seq 243.4 212.3 12.28 29.35 33.11 pdc 32.4 19.2 7.67 29.19 32.33 misex3 16.8 15.1 16.87 15.83 19.78 exp5p 194.3 187.4 18.60 32.47 39.04 ex1010 101.9 25.9 9.92 59.95 67.53 des 22.2 20.9 8.10 16.20 17.65 apex4 82.4 34.6 1.26 39.75 40.13 apex2 42.7 22.8 6.45 35.29 38.20 alu4 with without with without Runtime (seconds) Impr. (%) Dynamic Power (mW) Circuits

Results

7.70 12.58 23.41 average 8.27 6.67 13.82 C880 9.74 13.98 21.32 C7552 9.23 22.84 18.05 C6288 7.42 11.10 18.82 C5315 8.62 17.75 33.45 C499 6.62 9.93 21.82 C432 9.99 14.21 20.92 C3540 4.68 6.57 19.09 C2670 7.62 11.52 21.25 C1908 7.80 15.22 34.76 C1355 7.50 10.96 16.17 spla 4.50 6.96 26.77 seq 7.29 15.26 31.63 pdc 6.36 9.35 28.43 misex3 8.43 21.02 25.79 exp5p 9.41 22.94 28.50 ex1010 8.44 11.94 20.81 des 7.10 10.18 20.35 apex4 9.45 5.23 7.48 apex2 5.51 8.01 38.89 alu4 Increase in Wire Length (%) Reduction in Switching Activity (%) Reduction in Glitch Power (%) Circuits

Conclusions

Glitch reduction in FPGA through routing

CAD approach, not require architectural modification 9.8% average of dynamic power reduction

Efficient Path-finding algorithm

A small, efficient subset of possible paths

Can be combined with other techniques

GlitchMap GlitchLess