A Practical Transmit/Receive System for Software Radio SDR Forum - PowerPoint PPT Presentation

A Practical Transmit/Receive System for Software Radio SDR Forum Technical Conference 2004 16 November 2004

Overview The Design Task System Components Design Partitioning Test System Results and Conclusions 15/11/2004 Slide 2 UNCLASSIFIED

The Design Task Design: • Test system to switch between two disparate modulation schemes under software control Evaluate: • Design Partitioning • Power Efficiency • FPGA Usage 15/11/2004 Slide 3 UNCLASSIFIED

System Components Digital RX/TX • Reconfigurable • Flexible • Modular Mezzanine card (PMC) PCI Bus Embedded DSP 15/11/2004 Slide 4 UNCLASSIFIED

Design Partitioning DSP FPGA FPGA or DSP DIGITAL BASEBAND • Flexibility vs Speed RECEIVER PROCESSING • Power Considerations Battery Restrictions Conduction Cooled environment • FPGA availability • Data Rates Decimation/Oversampling 15/11/2004 Slide 5 UNCLASSIFIED

Test System Modulation: RAD-T2 RAD-2 • QAM and FSK Digital TX Digital RX (PMC) (PMC) • Widely used • Disparate schemes Generated DATA Captured DATA Command & Control Design: • Maximum Use of PMCs PMC1 PMC2 Embedded Processor VME Base-board • No complex coding • Command line control – Data Display via laptop. Modulation type Data selection Frequency Laptop 15/11/2004 Slide 6 UNCLASSIFIED

Transmitter (1) QAM • DAC intrinsic capability • FPGA Data generation QAM Symbol mapping QAM DAC FPGA Interleaving Pre-Conditioning 64 bit 66MHz PCI Data Generation o l 14 Bit C o n t r & QAM Interleaved DAC Symbol Modulator Data Mapping System Clock 15/11/2004 Slide 7 UNCLASSIFIED

Transmitter (2) FSK • Modulating internal NCO • FPGA Preset Frequencies Generate Data QAM DAC FPGA Presets MSK 64 bit 66MHz PCI Control Data Generation DAC NCO 1 bit Data System Clock F/MSK 15/11/2004 Slide 8 UNCLASSIFIED

Receiver (1) QAM Recovery FPGA SAMPLE CLK F I LPF 64 bit 66MHz PCI F DATA DATA O Clock & 90 ADC Symbol Recovery LPF COMMAND/CONTROL NCO TUNE QAM demodulator • Standard design • Single channel, 16-bit, 66MHz Fs • Decimation and filtering on-board 15/11/2004 Slide 9 UNCLASSIFIED

Receiver (2) FPGA FSK Recovery F SAMPLE CLK I 64 bit 66MHz PCI F DATA DATA O Data Formatting ADC COMMAND/CONTROL MSK ‘demodulator’ • could use QAM demod Straight digitizer • tests max data rates 15/11/2004 Slide 10 UNCLASSIFIED

Results Power • < 7W dissipation before modifications • QAM demod exhibits most power dissipation Maximum additional power 2W Real Estate • ~10% of 3M FPGA in use before modifications • QAM demod largest circuit requirements Adds 7% to circuit design Signal Performance 15/11/2004 Slide 11 UNCLASSIFIED

Conclusions Signal conditioning required close to conversion Careful consideration of design partitioning • Speed • Flexibility • Power • Real-Estate • Available Time PMC format good vehicle to deliver digitising and conditioning • Multiple DSP/FPGA cards available in VME. 15/11/2004 Slide 12 UNCLASSIFIED

Contact Details Doug Moore Pentland Systems 1b Young Square Brucefield Industry Park Livingston West Lothian EH54 9BX doug.moore@pentland.co.uk http://www.pentlandsys.com Tel: +44-1506-464666 Fax: +44-1506-463030 Come and talk to us in the Exhibits room 15/11/2004 Slide 13 UNCLASSIFIED