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A Practical Transmit/Receive System for Software Radio SDR Forum - - PowerPoint PPT Presentation
A Practical Transmit/Receive System for Software Radio SDR Forum - - PowerPoint PPT Presentation
A Practical Transmit/Receive System for Software Radio SDR Forum Technical Conference 2004 16 November 2004 Overview The Design Task System Components Design Partitioning Test System Results and Conclusions 15/11/2004 Slide 2
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The Design Task
Design:
- Test system to switch between two
disparate modulation schemes under software control
Evaluate:
- Design Partitioning
- Power Efficiency
- FPGA Usage
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System Components
Digital RX/TX
- Reconfigurable
- Flexible
- Modular
Mezzanine card (PMC) PCI Bus
Embedded DSP
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Design Partitioning
FPGA or DSP
- Flexibility vs Speed
- Power Considerations
Battery Restrictions Conduction Cooled environment
- FPGA availability
- Data Rates
Decimation/Oversampling
DIGITAL RECEIVER BASEBAND PROCESSING
FPGA
DSP
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Test System
Modulation:
- QAM and FSK
- Widely used
- Disparate schemes
Design:
- Maximum Use of PMCs
- No complex coding
- Command line control –
via laptop.
RAD-T2 Digital TX (PMC)
Embedded Processor VME Base-board
RAD-2 Digital RX (PMC)
Generated DATA Captured DATA
Command & Control
Laptop Modulation type Data selection Frequency
Display Data PMC1 PMC2
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Transmitter (1)
QAM
- DAC intrinsic capability
- FPGA
Data generation Symbol mapping Interleaving Pre-Conditioning
FPGA Data Generation & Symbol Mapping
C
- n
t r
- l
System Clock 64 bit 66MHz PCI QAM
QAM DAC
DAC
14 Bit Interleaved Data QAM Modulator
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Transmitter (2)
FSK
- Modulating internal NCO
- FPGA
Preset Frequencies Generate Data MSK
FPGA Data Generation
Control
System Clock 64 bit 66MHz PCI
QAM DAC
DAC
Presets NCO 1 bit Data F/MSK
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Receiver (1)
QAM demodulator
- Standard design
- Single channel, 16-bit, 66MHz Fs
- Decimation and filtering on-board
FPGA LPF LPF 90 NCO Clock & Symbol Recovery F I F O
DATA COMMAND/CONTROL
TUNE 64 bit 66MHz PCI
DATA
ADC
SAMPLE CLK
QAM Recovery
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Receiver (2)
MSK ‘demodulator’
- could use QAM demod
Straight digitizer
- tests max data rates
FPGA ADC
SAMPLE CLK
Data Formatting F I F O
DATA COMMAND/CONTROL
64 bit 66MHz PCI
DATA
FSK Recovery
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Results
Power
- < 7W dissipation before modifications
- QAM demod exhibits most power dissipation
Maximum additional power 2W
Real Estate
- ~10% of 3M FPGA in use before
modifications
- QAM demod largest circuit requirements
Adds 7% to circuit design
Signal Performance
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Conclusions
Signal conditioning required close to conversion Careful consideration of design partitioning
- Speed
- Flexibility
- Power
- Real-Estate
- Available Time
PMC format good vehicle to deliver digitising and conditioning
- Multiple DSP/FPGA cards available in VME.
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