A Highly Integrated 65-nm SoC Process with Enhanced - - PowerPoint PPT Presentation

▶
a highly integrated 65 nm soc process with enhanced power
SMART_READER_LITE
LIVE PREVIEW

A Highly Integrated 65-nm SoC Process with Enhanced - - PowerPoint PPT Presentation

Oct 05, 2023 227 likes •505 views

A Highly Integrated 65-nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits L. T. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K. Fujita*, P. Gregory, T. Hoffmann, M. Hori*, D. Kanai*, D. Kidd, S. Lee, Y.

slide-1
SLIDE 1

A Highly Integrated 65-nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits

  • L. T. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K.

Fujita*, P. Gregory, T. Hoffmann, M. Hori*, D. Kanai*, D. Kidd, S. Lee,

  • Y. Liu, J. Mitani*, J. Nagayama*, S. Pradhan, P. Ranade, R.

Rogenmoser, L. Scudder, L. Shifren, Y. Torii*, M. Wojko, Y. Asada*, T. Ema*, and S. Thompson

SuVolta, Inc. *Fujitsu Semiconductor Ltd

1

slide-2
SLIDE 2

Presentation Outline

  • Low-power SoC platform
  • Process and device results
  • Circuit results

– SRAM VDDmin reduction – Digital logic power reduction – Analog matching and performance

  • Conclusions

2

slide-3
SLIDE 3

Low-Power SoC Platform

  • Significantly extends 65/55-nm node life with

enhanced functionality

  • Lower cost alternative to 40-nm migration

ARM M-0 200MHz @ 0.6V

  • VDDmin ~400mV
  • Lower ISB
  • 4X Rout
  • 2x better AVT

Transistor level benefits

  • Higher drive current
  • Tighter VT control
  • Seamless integration to baseline

Product level benefits

  • VDD reduction from 1.2V to 0.9V

– Nearly half power and matched delay

  • Extended voltage range

– Improved low voltage yield

3

slide-4
SLIDE 4

Presentation Outline

  • Low-power SoC platform
  • Process and device results
  • Circuit results

– SRAM VDDmin reduction – Digital logic power reduction – Analog matching and performance

  • Conclusions

4

slide-5
SLIDE 5

Deeply Depleted Channel (DDC)

  • Seamless integration into baseline process
  • Legacy devices supported

– Legacy IP support possible

5

  • 65-nm example transistor
slide-6
SLIDE 6

DDC Matching Benefits

  • Improved transistor matching

– Un-doped channel

  • Better RDF

– Epitaxial channel formed after wells

  • No well proximity effects

– Excellent VT Control – No halo implants

  • Further improves RDF
  • No halo proximity effects
  • Epi layer thickness control

– Wafer: 1σ = 0.25% – Overall 1σ = 0.65%

26.9 27.3 Thickness (nm)

6

slide-7
SLIDE 7

DDC IEFF Increase

  • Better SCE

– Thinner tOX – DIBL reduced ~50mV/V – Higher low VDD mobility

  • IEFF w/ same

– LE – IOFF

7

0.6 0.7 0.8 0.9 1.0 1.1 1.2 10 20 30 40 50 60

DDC IEFF gain (%) VDD (V)

slide-8
SLIDE 8

Threshold Voltage Control

  • Enables better systematic corners

Logic Device SRAM

0.50 0.45 0.40

  • 0.50
  • 0.45
  • 0.40
  • 0.35

DDC Control

3σ 1σ 2σ

PMOS VT (V) NMOS VT (V)

0.3 0.7 0.70 0.4 0.5 0.6 0.65 0.60 0.55 0.50 0.45

PMOS VT (V) NMOS VT (V)

DDC Control

8

slide-9
SLIDE 9
  • 0.6 -0.4 -0.2 0.0

0.2 0.4 0.6 10 20 30 40 50 σ∆ σ∆ σ∆ σ∆Vt/2

0.5 (mV)

VT(V)

SRAM Transistor Matching

  • Better SRAM matching: Lower SRAM VDDmin
  • DDC σ

σ σ σ∆VT invariant across VT range

~60% ~40%

  • 0.55 -0.47 -0.39

0.36 0.40 0.44 10 20 30 40 50 σ∆ σ∆ σ∆ σ∆Vt/2

0.5 (mV)

VT (V)

9

slide-10
SLIDE 10

Junction Leakage

  • Ijunction well controlled, consistent across

VT range

0.30 0.35 0.40 0.45 0.50 1 10 100

NMOS leakage (pA/um) (L = 1µ

µ µ µm)

VT (V)

  • 0.2
  • 0.3
  • 0.4
  • 0.5

1 10 100

PMOS leakage (pA/um) (L = 1µ

µ µ µm)

VT (V)

10

slide-11
SLIDE 11

DDC Enhanced Body Effect

  • Highly doped screen layer increases body

coefficient by ~4x to ~7x

  • Allows significant process corner pull-in

ION Ioff

FF SS TT

50 100 150 200 250 300

PMOS NMOS

Logic

Body factor (mV/V)

Control DDC

SRAM

NMOS PMOS 11

slide-12
SLIDE 12

Corner Pull-in in Action

NMOS PMOS

12

slide-13
SLIDE 13

Presentation Outline

  • Low-power SoC platform
  • Process and device results
  • Circuit results

– SRAM VDDmin reduction – Digital logic power reduction – Analog matching and performance

  • Conclusions

13

slide-14
SLIDE 14

SRAM VDDmin Improvement

  • No circuit changes from baseline—same masks

– 6-T 9.4Mb arrays – No redundancy

14

0.2 0.4 0.6 0.8 1.0 1.2 1.4 10 20 30 40 50 60 70 80 90 100

  • 40C

RT 125C

% Yield (9.4 Mb) VDD (V)

slide-15
SLIDE 15

Circuit Logic Corner Pull-in

  • Inverter ring oscillator measurements
  • Baseline VDD = 1.2V
  • DDC VDD = 0.9V
  • SS frequency

400MHz to 150MHz by adjusting BB

  • FF frequency

500MHz to 200MHz by adjusting BB

100 200 300 400 500 600 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45

Control DDC SS DDC TT DDC FF

Total power (mW) Frequency (MHz)

SS@ Vbb=0V FF@ Vbb=-0.8V

15

slide-16
SLIDE 16

No Body Effect Stack Penalty

  • Higher low VDS IEFF

counteracts body bias impact in stacks

  • Ring oscillator

– NAND (NMOS stack) NOR (PMOS stack) gates are faster than baseline

  • DDC VDD = 0.9V
  • Control VDD = 1.2V

2 3 4 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Relative RO Frequency (normalized to inverter) Number of Inputs

NAND DDC NOR DDC NAND Control NOR Control

16

slide-17
SLIDE 17

200 400 600 0.0 0.1 0.2 0.3 0.4 0.5 0.6

Total power (mW) Frequency (MHz)

Logic Power Reduction with DDC

  • Inverter ring oscillator
  • Sweep VDD and

reverse body bias

  • 38% greater

performance at same total power

  • 47% less power at

same performance

38% 47%

17

slide-18
SLIDE 18

Logic Power Reduction with DDC

  • Large logic/SRAM embedded block
  • 5.8M gates
  • 1.45Mb SRAM
  • Same mask set
  • 47% less power at

same performance

– Control VDD = 1.2V – DDC VDD = 0.9V

18

0.0 0.2 0.4 0.6 0.8 1.0

DDC with Vbb

VDD = 0.9V

Normalized Power dissipation

Dynamic Static Control VDD = 1.2V

slide-19
SLIDE 19

ARM M-0 Core Results

  • Preliminary results

– DDC implementation achieves 200 MHz @ VDD = 0.6V

  • Body bias selection not optimized

19

slide-20
SLIDE 20

Presentation Outline

  • Low-power SoC platform
  • Process and device results
  • Circuit results

– SRAM VDDmin reduction – Digital logic power reduction – Analog matching and performance

  • Conclusions

20

slide-21
SLIDE 21

DDC Analog Benefits

  • Higher IEFF
  • Reduced VDsat
  • Higher RDS
  • Improved

matching

21

0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0

DDC Control

NMOS IDS (mA)

VDS (V)

slide-22
SLIDE 22

DDC Analog Circuit Improvement

  • Matching improved by

– Local: 40% NMOS, 30% PMOS – Global: 40% NMOS, 30% PMOS

  • Current mirrors

– 16x current gain

22

slide-23
SLIDE 23

DDC Analog Circuit Improvement

  • Differential Amplifier

DC measurements

– DDC VDD = 1.2V and Control VDD = 0.9V

  • 20
  • 10

10 20 0.0 0.2 0.4 0.6 0.8 1.0 1.2

Output voltage (V) Input offset (mV)

Control DDC

23

slide-24
SLIDE 24

DDC Analog Circuit Improvement

  • OTA DC measurements
  • Gain improved 12dB

– More consistent gain – Same layout

  • Better matching

allows smaller analog circuits

– Reduced loading – Better slew rate

24

slide-25
SLIDE 25

Presentation Outline

  • Low-power SoC platform
  • Process and device results
  • Circuit results

– SRAM VDDmin reduction – Digital logic power reduction – Analog matching and performance

  • Conclusions

25

slide-26
SLIDE 26

Conclusions

  • DDC 65/55-nm SOC process

– Nominal VDD scaled to 0.9V from 1.2V—up to 47% power savings – Proven on large logic/memory blocks – ARM M-0 core operates at 200 MHz at VDD = 0.6V

  • 6-T SRAM VDDmin below 400mV demonstrated on 9.4Mb

arrays

– Un-doped channel mitigates RDF – No halo, well proximity effects

  • Enhanced body effect

– Allows effective logic corner pull-in with body biasing

  • Improved analog circuit matching and gain
  • Processing compatible with multi-VT and legacy devices

– Straightforward support for existing IP

26

slide-27
SLIDE 27

Thank You for Your Attention

  • Questions?

27