- 3. Bipolar Junction Transistor (BJT)
ECE 65, Winter 2013, F. Najmabadi
3. Bipolar Junction Transistor (BJT) Lecture notes: Sec. 3 Sedra - - PowerPoint PPT Presentation
3. Bipolar Junction Transistor (BJT) Lecture notes: Sec. 3 Sedra & Smith (6 th Ed): Sec. 6.1-6.4* Sedra & Smith (5 th Ed): Sec. 5.1-5.4* * Includes details of BJT device operation which is not covered in this course ECE 65, Winter 2013,
ECE 65, Winter 2013, F. Najmabadi
An implementation on an IC
Simplified physical structure
does NOT act as two diodes back to back when voltages are applied to all three terminals.
the other four:
CE BE BC B C E
v v v i i i − = + = : KVL : KCL Circuit symbol and Convention for current directions (Note: vCE = vC – vE)
among (iB , iC , vBE , and vCE )
) , ( ) (
CE B C BE B
v i g i v f i = =
Active mode:
/ / D CE V v S C V v S C B
V v e I i e I i i
T BE T BE
≥ = = = β β
near the depletion region of BC junction and are swept into the collector if vCB ≥ 0 (vBC ≤ 0 : BC junction is reverse biased!)
(and vCE ) as long as
T BE V
v S C
e I i
/
=
D CE CE D CE BE BC
V v v V v v v ≥ ≤ − = − =
As Emitter is heavily doped, a large number of electrons diffuse into the base (only a small fraction combine with holes) The number of these electrons scales as
T BE V
v
e
/
BE junction is forward biased (vBE = VD0)
(and thus, iC ): iB = iC/β
T BE V
v
e
/
and a diffusion current will set up, reducing iC .
vBC ≤ 0.4 V (Si), diffusion current is small and iC is very close to its active-mode level.
its active-mode level (iC < β iB).
circuit & does not respond to changes in iB.
Both iC & iB are close to zero. Similar to the active mode, a large number of electrons diffuse into the base. BE junction is forward biased (vBE = VD0) “Deep” Saturation mode:
sat CE B C V v S B
V v i i e I i
T BE
≈ < =
/
β β
* Sedra & Smith includes this in the active region, i.e., BJT is in active mode as long as vCE ≥ 0.3 V.
iB
Cut-off : BE is reverse biased
, = =
C B
i i
Active*: BE is forward biased BC is reverse biased
B C
i i β =
Saturation: BE is forward biased, BC is forward biased
B C CE
i i v , V 7 . 3 . β ≈ ≤ ≤
B C CE
i i v , V 3 . 1 . β < ≤ ≤ , V 1 . ≈ ≤
C CE
i v
* Plot includes early effect (slide 8)
Looking at surface with iB axis pointing out of the paper
* Saturation region is exaggerated in 3D picture for clarity
different iB (or vBE ) coincide at vCE = − VA + =
A CE V v S C
V v e I i
T BE
1
/
“Linear” model* Cut-off :
BE is reverse biased
Active:
BE is forward biased BC is reverse biased
(Deep) Saturation:
BE is forward biased BC is foward biased
, = =
C B
i i ,
D BE C B
V v i i < = = + = = =
A CE V v S C V v S C B
V v e I i e I i i
T BE T BE
1
/ /
β β , ,
D CE B C B D BE
V v i i i V v ≥ = ≥ = β
B C sat CE V v S B
i i V v e I i
T BE
,
/
β β < ≈ =
B C sat CE B D BE
i i V v i V v , , β < = ≥ = V 2 . , V 7 . Si, For = =
sat D
V V * BJT Linear model is based on a diode “constant-voltage” model for the BE junction and ignores Early effect.
Compared to a NPN: 1) Current directions are reversed 2) Voltage subscripts “switched”
“Linear” model Cut-off :
EB is reverse biased
Active:
EB is forward biased CB is reverse biased
(Deep) Saturation:
EB is forward biased CB is foward biased
,
D EB C B
V v i i < = = , ,
D EC B C B D EB
V v i i i V v ≥ = ≥ = β
B C sat EC B D EB
i i V v i V v , , β < = ≥ =
DC voltages: Use “Double subscript” of BJT terminal: VCC , VBB , VEE . Resistors: Use “subscript” of BJT terminal: RC , RB , RE . Voltage sources are identified by node voltage!
Controller part: Circuit connected to BE sets iB Controlled part: iC & vCE are set by transistor state (&
iC = 0
iC < β iB iC is limited by circuit connected to CE terminals, increasing iB does not increase iC
a. BJT OFF: Set iC = 0, use CE-KVL to find vCE (Done!) b. BJT ON: Compute iB 3. Assume BJT in active. Set iC = β iB . Use CE-KVL to find vCE . If vCE ≥ VD0 , Assumption Correct, otherwise in saturation:
simultaneously.
CE C BE B
v i v i + = + × = 10 12 : KVL
10 40 4 : KVL
3 3
incorrect Assumption V 7 . V 4 V 4 10 40 4 : KVL
V 7 . and :
Assume
3
→ = > = = → + × × = = < =
D BE BE BE D BE B
V v v v V v i A 5 . 82 7 . 10 40 4 : KVL
and V 7 . : ON BE
3
> = → + × × = ≥ = = µ
B B B D BE
i i i V v correct Assumption V 7 . V 75 . 3 V 75 . 3 10 25 . 8 10 12 : KVL
mA 25 . 8 10 25 . 8 100 V 7 . and : Active Assume
3 3 6
→ = > = = → + × × = = × × = = = ≥ =
− − D CE CE CE B C D CE B C
V v v v i i V v i i β β
CE C C CC BE B B i
v i R V v i R v + = + = : KVL
: KVL
: KVL
: KVL
and :
CC CE CE C CC C i BE BE B i D BE B
V v v R V i v v v R v V v i = → + × = = = → + × = < = , , Cutoff in BJT For
CC CE C B D i
V v i i V v = = = → < : KVL
and : ON BE
D i B B D i B D B B i B D BE
V v i R V v i V i R v i V v ≥ → ≥ − = → + × = ≥ =
CE C C CC B D i B D BE
v i R V R V v i V v + = − = = : KVL
and : ON BE
B C D CC D i D CE C C CC CE CE C C CC B D i C D CE B c
R R V V V v V v i R
v v i R V R V v i V v i i / : KVL
and : Active β β β − + ≤ → ≥ = → + = − × = ≥ = active in BJT / For → − + ≤ ≤
B C D CC D i D
R R V V V v V β
CE C C CC B D i B D BE
v i R V R V v i V v + = − = = : KVL
and : ON BE
B C sat CC D IH i B c C sat CC C sat C C CC B c sat CE
R R V V V V v i i R V
i V i R V i i V v / : KVL
and : n Saturaatio β β β − + = > → < = → + = < = saturation in BJT / For → < − +
i B C D CC D
v R R V V V β
saturation deep in BJT / active in BJT / Cutoff in BJT → < − + → − + ≤ ≤ → <
i B C sat CC D B C D CC D i D D i
v R R V V V R R V V V v V V v β β
C C CC CE
i R V v ) KVL
Line Load − = together increase & : Active
C B IH i D
i i V v V ≤ ≤ unchanged but increases : Saturation
C B i IH
i i v V < :
Cut
D i
V v < −
*Lab 4 circuit Solved in Lecture notes (problems 12 & 13) Load is placed in collector circuit
logic circuits because of
RTL NOT gate (VL = Vsat , VH = VCC) Resistor-Transistor logic (RTL) RTL NOR gate* RTL NAND gate* *Solved in Lecture notes (problems 14 & 15)
typically gives a range as well as an average value for β )
includes temperature and iC dependence).
deep saturation for all similar model BJTs, we need to set iC /iB < βmin