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Y86 encoding / SEQ part 1 1 last time instruction set (interface) v microarchitecture (implementation) RISC (simpler HW) v CISC (more fmexible ASM) Y86-64 ISA started Y86 encoding 3 Y86-64 instruction formats 9 0 rA rB OP q rA, rB 6 fn rA

  1. Y86 encoding / SEQ part 1 1

  2. last time instruction set (interface) v microarchitecture (implementation) RISC (simpler HW) v CISC (more fmexible ASM) Y86-64 ISA started Y86 encoding 3

  3. Y86-64 instruction formats 9 0 rA rB OP q rA, rB 6 fn rA rB j CC Dest 7 cc call Dest 8 0 ret 0 mrmovq D(rB), rA pushq rA A 0 rA F popq rA B 0 rA F V D D Dest Dest 5 0 rA rB byte: halt 0 1 2 3 4 5 6 7 8 9 0 4 0 nop 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 3 0 F rB rmmovq rA, D(rB) 4

  4. Secondary opcodes: cmov cc / j cc B j CC Dest 7 cc call Dest 8 0 ret 9 0 pushq rA A 0 rA F popq rA 0 rA F 6 V D D Dest Dest 0 always ( jmp / rrmovq ) 1 le 2 l 3 e 4 ne 5 ge 6 g fn rA rB OP q rA, rB byte: 0 0 1 2 3 4 5 6 7 8 9 halt 0 nop 0 rA rB 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 3 0 F rB rmmovq rA, D(rB) 4 0 rA rB mrmovq D(rB), rA 5 5

  5. Secondary opcodes: OP q B j CC Dest 7 cc call Dest 8 0 ret 9 0 pushq rA A 0 rA F popq rA 0 rA F 6 V D D Dest Dest 0 add 1 sub 2 and 3 xor fn rA rB OP q rA, rB byte: 0 0 1 2 3 4 5 6 7 8 9 halt 0 nop 0 rA rB 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 3 0 F rB rmmovq rA, D(rB) 4 0 rA rB mrmovq D(rB), rA 5 6

  6. Registers: rA, rB 8 %rdx 2 %r9 9 %rcx 1 %r8 %rax %r10 0 Dest Dest D D V 0 rA F B A 3 0 rA F %r13 none F %rdi 7 %r14 E %rsi 6 D %rbx %rbp 5 %r12 C %rsp 4 %r11 B popq rA A byte: 9 rrmovq / cmovCC rA, rB 0 1 nop 0 0 halt 8 irmovq V, rB 7 6 5 4 3 2 1 0 2 cc rA rB 3 pushq rA fn rA rB 0 9 ret 0 8 call Dest 7 cc j CC Dest 6 0 OP q rA, rB 0 rA rB 5 mrmovq D(rB), rA 0 rA rB 4 rmmovq rA, D(rB) F rB 7

  7. Immediates: V, D, Dest 9 0 rA rB OP q rA, rB 6 fn rA rB j CC Dest 7 cc call Dest 8 0 ret 0 mrmovq D(rB), rA pushq rA A 0 rA F popq rA B 0 rA F V D D Dest Dest 5 0 rA rB byte: halt 0 1 2 3 4 5 6 7 8 9 0 4 0 nop 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 3 0 F rB rmmovq rA, D(rB) 8

  8. Immediates: V, D, Dest 9 0 rA rB OP q rA, rB 6 fn rA rB j CC Dest 7 cc call Dest 8 0 ret 0 mrmovq D(rB), rA pushq rA A 0 rA F popq rA B 0 rA F V D D Dest Dest 5 0 rA rB byte: halt 0 1 2 3 4 5 6 7 8 9 0 4 0 nop 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 3 0 F rB rmmovq rA, D(rB) 8

  9. Y86-64 encoding (1) long addOne( long x) { return x + 1; } x86-64: movq %rdi, %rax addq $1, %rax ret Y86-64: irmovq $1, %rax addq %rdi, %rax ret 9

  10. Y86-64 encoding (1) long addOne( long x) { return x + 1; } x86-64: movq %rdi, %rax addq $1, %rax ret Y86-64: irmovq $1, %rax addq %rdi, %rax ret 9

  11. Y86-64 encoding (2) addOne: irmovq $1, %rax addq %rdi, %rax ret 3 0 F %rax 01 00 00 00 00 00 00 00 30 F0 01 00 00 00 00 00 00 00 60 70 90 10 ⋆

  12. Y86-64 encoding (2) addOne: irmovq $1, %rax addq %rdi, %rax ret 3 0 F 0 01 00 00 00 00 00 00 00 30 F0 01 00 00 00 00 00 00 00 60 70 90 10 ⋆

  13. Y86-64 encoding (2) addOne: 30 F0 01 00 00 00 00 00 00 00 60 70 90 %rax %rdi add 6 01 00 00 00 00 00 00 00 0 F 0 3 ret %rdi, %rax addq %rax $1, irmovq 10 ⋆

  14. Y86-64 encoding (2) addOne: 30 F0 01 00 00 00 00 00 00 00 60 70 90 0 7 0 6 01 00 00 00 00 00 00 00 0 F 0 3 ret %rdi, %rax addq %rax $1, irmovq 10 ⋆

  15. Y86-64 encoding (2) addOne: 30 F0 01 00 00 00 00 00 00 00 60 70 90 0 9 0 7 0 6 01 00 00 00 00 00 00 00 0 F 0 3 ret %rdi, %rax addq %rax $1, irmovq 10 ⋆

  16. Y86-64 encoding (2) 0 30 F0 01 00 00 00 00 00 00 00 60 70 90 0 9 0 7 0 6 01 00 00 00 00 00 00 00 F addOne: 0 3 ret %rdi, %rax addq %rax $1, irmovq 10

  17. Y86-64 encoding (3) doubleTillNegative: addq %rax, %rax jge doubleTillNegative 6 add %rax %rax 11 /* suppose at address 0x123 */

  18. Y86-64 encoding (3) doubleTillNegative: addq %rax, %rax jge doubleTillNegative 6 add %rax %rax 11 /* suppose at address 0x123 */ ⋆

  19. Y86-64 encoding (3) doubleTillNegative: addq %rax, %rax jge doubleTillNegative 6 0 0 0 11 /* suppose at address 0x123 */ ⋆

  20. Y86-64 encoding (3) doubleTillNegative: addq %rax, %rax jge doubleTillNegative 6 0 0 0 7 5 23 01 00 00 00 00 00 00 11 /* suppose at address 0x123 */

  21. Y86-64 encoding (3) doubleTillNegative: addq %rax, %rax jge doubleTillNegative 6 0 0 0 7 5 23 01 00 00 00 00 00 00 11 /* suppose at address 0x123 */ ⋆

  22. Y86-64 encoding (3) doubleTillNegative: addq %rax, %rax jge doubleTillNegative 6 0 0 0 7 5 23 01 00 00 00 00 00 00 11 /* suppose at address 0x123 */

  23. Y86-64 decoding ret 0 rA rB mrmovq D(rB), rA 5 0 rA rB OP q rA, rB 6 fn rA rB j CC Dest 7 cc call Dest 8 0 9 rmmovq rA, D(rB) 0 pushq rA A 0 rA F popq rA B 0 rA F V D D Dest Dest 4 F rB 20 10 60 20 61 37 72 84 00 00 00 00 00 00 00 byte: 20 12 20 01 70 68 00 00 00 00 00 00 00 rrmovq %rcx, %rax addq %rdx, %rax subq %rbx, %rdi jl 0x84 rrmovq %rcx, %rdx rrmovq %rax, %rcx jmp 0x68 0 0 1 2 3 4 5 6 7 8 9 halt 0 0 nop 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 3 12

  24. Y86-64 decoding ret 0 rA rB mrmovq D(rB), rA 5 0 rA rB OP q rA, rB 6 fn rA rB j CC Dest 7 cc call Dest 8 0 9 rmmovq rA, D(rB) 0 pushq rA A 0 rA F popq rA B 0 rA F V D D Dest Dest 4 F rB 20 10 60 20 61 37 72 84 00 00 00 00 00 00 00 byte: 20 12 20 01 70 68 00 00 00 00 00 00 00 rrmovq %rcx, %rax addq %rdx, %rax subq %rbx, %rdi jl 0x84 rrmovq %rcx, %rdx rrmovq %rax, %rcx jmp 0x68 0 0 1 2 3 4 5 6 7 8 9 halt 0 0 nop 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 3 12

  25. Y86-64 decoding 0 4 0 rA rB mrmovq D(rB), rA 5 0 rA rB OP q rA, rB 6 fn rA rB j CC Dest 7 cc call Dest 8 ret F rB 9 0 pushq rA A 0 rA F popq rA B 0 rA F V D D Dest Dest rmmovq rA, D(rB) 0 20 10 60 20 61 37 72 84 00 00 00 00 00 00 00 3 20 12 20 01 70 68 00 00 00 00 00 00 00 rrmovq %rcx, %rax addq %rdx, %rax subq %rbx, %rdi jl 0x84 rrmovq %rcx, %rdx rrmovq %rax, %rcx jmp 0x68 byte: 0 irmovq V, rB 2 cc rA rB rrmovq / cmovCC rA, rB 0 1 nop 0 0 halt 2 3 4 5 6 7 8 9 1 12 ◮ 0 as cc: always ◮ 1 as reg: %rcx ◮ 0 as reg: %rax

  26. Y86-64 decoding 0 4 0 rA rB mrmovq D(rB), rA 5 0 rA rB OP q rA, rB 6 fn rA rB j CC Dest 7 cc call Dest 8 ret F rB 9 0 pushq rA A 0 rA F popq rA B 0 rA F V D D Dest Dest rmmovq rA, D(rB) 0 20 10 60 20 61 37 72 84 00 00 00 00 00 00 00 3 20 12 20 01 70 68 00 00 00 00 00 00 00 rrmovq %rcx, %rax addq %rdx, %rax subq %rbx, %rdi jl 0x84 rrmovq %rcx, %rdx rrmovq %rax, %rcx jmp 0x68 byte: 0 1 2 3 4 5 6 7 8 9 halt 0 0 nop 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 12 ◮ 0 as fn: add ◮ 1 as fn: sub

  27. Y86-64 decoding 0 4 0 rA rB mrmovq D(rB), rA 5 0 rA rB OP q rA, rB 6 fn rA rB j CC Dest 7 cc call Dest 8 ret F rB 9 0 pushq rA A 0 rA F popq rA B 0 rA F V D D Dest Dest rmmovq rA, D(rB) 0 20 10 60 20 61 37 72 84 00 00 00 00 00 00 00 3 20 12 20 01 70 68 00 00 00 00 00 00 00 rrmovq %rcx, %rax addq %rdx, %rax subq %rbx, %rdi jl 0x84 0x84 rrmovq %rcx, %rdx rrmovq %rax, %rcx jmp 0x68 byte: 0 1 2 3 4 5 6 7 8 9 halt 0 0 nop 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 12 ◮ 2 as cc: l (less than) ◮ hex 84 00 … as little endian Dest:

  28. Y86-64 decoding ret 0 rA rB mrmovq D(rB), rA 5 0 rA rB OP q rA, rB 6 fn rA rB j CC Dest 7 cc call Dest 8 0 9 rmmovq rA, D(rB) 0 pushq rA A 0 rA F popq rA B 0 rA F V D D Dest Dest 4 F rB 20 10 60 20 61 37 72 84 00 00 00 00 00 00 00 byte: 20 12 20 01 70 68 00 00 00 00 00 00 00 rrmovq %rcx, %rax addq %rdx, %rax subq %rbx, %rdi jl 0x84 rrmovq %rcx, %rdx rrmovq %rax, %rcx jmp 0x68 0 0 1 2 3 4 5 6 7 8 9 halt 0 0 nop 1 0 rrmovq / cmovCC rA, rB 2 cc rA rB irmovq V, rB 3 12

  29. circuits: wires 0 0 1 1 0 0 1 1 1 1 binary value — actually voltage value propagates to rest of wire (small delay) 13

  30. circuits: wires 0 0 1 1 0 0 1 1 1 1 binary value — actually voltage value propagates to rest of wire (small delay) 13

  31. circuits: wires 0 0 1 1 0 0 1 1 1 1 binary value — actually voltage value propagates to rest of wire (small delay) 13

  32. circuits: wire bundles 1 26 26 same as 26 26 same as 11010 = 26 1 0 1 1 0 0 1 1 0 14

  33. circuits: wire bundles 1 26 26 same as 26 26 same as 11010 = 26 1 0 1 1 0 0 1 1 0 14

  34. circuits: wire bundles 1 26 26 same as 26 26 same as 11010 = 26 1 0 1 1 0 0 1 1 0 14

  35. circuits: gates 0 0 0 1 1 0 1 1 0 1 1 0 15

  36. circuits: logic want to do calculations? generalize gates: output wires contain result of function on input changes as input changes (with delay) need not be same width as output “logic” 12 function(12) = ?? 16

  37. circuits: logic want to do calculations? generalize gates: output wires contain result of function on input changes as input changes (with delay) need not be same width as output “logic” 12 function(12) = ?? 16

  38. circuits: logic want to do calculations? generalize gates: output wires contain result of function on input changes as input changes (with delay) need not be same width as output “logic” 12 function(12) = ?? 16

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