SLIDE 1
Lyon Mai 2012 D.Charlet
XTCA for SuperB project
- FTCS
- ECS
SuperB XTCA – CERN Lyon 0512 D.Charlet
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XTCA for SuperB project FTCS ECS Lyon Mai 2012 D.Charlet SuperB - - PowerPoint PPT Presentation
XTCA for SuperB project FTCS ECS Lyon Mai 2012 D.Charlet SuperB - - PowerPoint PPT Presentation
XTCA for SuperB project FTCS ECS Lyon Mai 2012 D.Charlet SuperB detector SuperB detector 2 D.Charlet SuperB XTCA CERN Lyon 0512 FCTS requirements FCTS requirements Synchronizing the experiment with the machine.
SLIDE 2
SLIDE 3
SuperB XTCA – CERN Lyon 0512 D.Charlet
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FCTS requirements FCTS requirements
Synchronizing the experiment with the machine. Delivering and buffering the clock to the experiment. Dealing with the raw L1 trigger decision. Throttling the latter. Permits the partitioning the system into independent subsystems or
groups of subsystems.
Generating programmable local trigger for calibration and
commissioning.
Generating different commands (calibration pulse, reset, BxID and event
ID).
Managing the stack of IP addresses for PC farm. Keeping trace of all event-linked data to put in the event readout
SLIDE 4
SuperB XTCA – CERN Lyon 0512 D.Charlet
4
Overall system achitecture
… L1 processor Drift Chamber … … EMC SVT
?
Global Level1 Trigger (GLT)
Detector
FE Boards L1 Buffer Ctrl
FE Electronics
pre-selection
Event data
FCTS interface Tx
Trigger primitives ROMs
Rx ~ 325 Optical links ~ 50 m
DAQ Crate
Crate Control
PCs Farm
Radiation wall
Raw L1 CLK, L1, Sync Cmds Clk, L1, Sync Cmds
Event fragments
Full Events Clk, L1, Sync Cmds Throttle Field Bus Detector Safety System Ethernet Throttle Ethernet …
FCTS
FEE models throttling L1 processor L1 processor Ethernet ECS interface Subdetector Specific Electronics Ethernet Ethernet ctrl
ECS
Ethernet Ethernet L3 to L5
~ 325 ~ 325 ~ 80 ~ 80 ~15
SLIDE 5
SuperB XTCA – CERN Lyon 0512 D.Charlet
5 FCTM 5
FCTS Architecture
Global Level 1 trigger(GLT)
Throttle Switch FCTS Switch EMC FE IFR FE SVT FE DHC FE PID FE
FCTS master : FCTM Fan-in / Fan-out : supports partitionning Front-End electronics
L1 Event building network FCTM 2 FCTM 1 ReadOut Board ReadOut Board ReadOut Board ReadOut Board ReadOut Board
ReadOut Module
Local trigger
Clock generator module
ECS Slow throttle
SLIDE 6
SuperB XTCA – CERN Lyon 0512 D.Charlet
FCTS architecture push concept
Fanout Agregate
FEE FEE
ROM ROM Fanout Agregate
FEE FEE
ROM ROM
ETHERNET SLOW TROTTLE SWITCH
FCTM
Stratix V FPGA
NIOS
10 GB SWITCH FCTM
Stratix V FPGA
NIOS
Cross bar Cde & Fast throttle link ROM cde dedicated link Data link Ethernet link L1 Trigger RF & FID
SLIDE 7
SuperB XTCA – CERN Lyon 0512 D.Charlet
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FCTS xTCA architecture
ARRIA V FPGA Crossbar 72 x 72 max 6.5 Gbits/s Cyclone III FPGA channels receivers 1 Gigabit Ethe transceive
Throttle switch board (AMC generic) NAT MCH (Tongues 1 and 2)
Supervisio
NIOS
Standard backplane (dual star layout)
Stratix V FPGA transceiver
FCTM board (AMC)
NIOS
1 mezzanine board mezzanine board
Switch board (Tongues 3 and 4)
Gigabit Ethernet Switch CPU
Ethernet link
SMA Clock distribution
Tongue 1 Tongue 2 Tongues 3 & 4
PHY ARRIA V FPGA channels receivers
Control link switch board (AMC generic)
NIOS 1
mezzanine board
SLIDE 8
SuperB XTCA – CERN Lyon 0512 D.Charlet
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FCTS Boards
Trigger type Trigger generation Ip destination broadcaster L1 Trigger rate Controller Fast throttle Ip & throttle From farm CCL computation & serialization Duplicator
Fast
Commands ECS ECS interface Clock Farm interface ECS interface Spy Event-linked Data Command broadcaster
B a c k p l a n e l i n k d u p l i c a t
- r
CCL L1 ECS Clock Trottle
Stratix V GX Stratix V GX
Event buffer DDR3 Event buffer DDR3 FLASH FLASH DDR3 DDR3 @ @ @ Data Data Data MMC MMC Clock out 12 serial links 8 serial links 2 PCIe links 1 GBe link PCIe Clock PLL PLL Clock In Optical Mezzanine Optical Mezzanine 36 serial links Jitter cleaner Jitter cleaner
ECS path
AMC connector
X_FPGA path TFC path
Throttle in, out Clock In and out
AMC mezzanine board (CCPM development) Example of optical mezzanine (CCPM development
SLIDE 9
SuperB XTCA – CERN Lyon 0512 D.Charlet
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Control & distribution module
L1 computation ? L1 Distributor L1 CLock Distributor ECS ECS Distributor Clock Clock generator ECS Interface Crate control
Machine Clock ECS Global Level 1 Trigger
INPUT OUTPUT
Tong 1: On the shelf industrial board. Tong 2 : CCPM board
SLIDE 10
SuperB XTCA – CERN Lyon 0512 D.Charlet
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Distribution & trottle
CCL duplicator & Delay alignment CCL Selection Clock ECS Interface ECS
Fast
commands
(from FTCMs) To FE To ROM Tranceiver
Serial Link computation
Tranceiver
Receiver
Control Link switch module
Throttle OR Switch Clock ECS Interface ECS Throttle Commands (to FCTMs)
Emitter From ROMs Tranceiver
Serial Link computation
Tranceiver
X_FPGA path
ARRIA V GX ARRIA V GX
FLASH FLASH QDR+ QDR+ @ @ Data Data MMC MMC Clock out 1 serial link 8 serial links 1 PCIe link 1 GBe link PCIe Clock Clock In
Optical or copper Interface Optical or copper Interface
serial links
ECS path
AMC connector
X_FPGA path TFC path
Throttle in, out Clock In and out I/O
Mezzanine AMC generic board
Throttle switch module
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SuperB XTCA – CERN Lyon 0512 D.Charlet
Open questions for FCTS
- FPGA transceiver latency.
- DS92Lv018 FPGA emulation.
- Fast throttle link (links type, number, location,...).
- Slow throttle latency (Ethernet UDP).
- 2 Clocks (CCPM MCH mezzanine manage one)
- FCTS crate form factor ATCA or ATCA for physics (due to the link number)
– CCPM AMC and MSC mezzanine.
SLIDE 12
SuperB XTCA – CERN Lyon 0512 D.Charlet
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ECS requirement
SPECS Slave SPECS Bus SPECS Slave Ethernet Bus
Caverne Baraks
Configuration system for individual boards located on the detector or crate located
in the cavern.
Located in radiation sensitive environment, up to 20KRad. Long distance link, up to 130m. Multi configuration (multi-drop bus, point to point). Multi standard interfaces (JTAG, I2C, parallel bus, ctrl I/O).
A A S Serial erial P Protocol for rotocol for E Experiment xperiment C Control
- ntrol S
System ystem SPECS SPECS
SLIDE 13
SuperB XTCA – CERN Lyon 0512 D.Charlet
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SuperB SPECS slave implementation
82mm 82mm 58mm 58mm
SPECS SLAVE MEZZANINE BOARD
SPEC S SLAV E
PR O
- ASICPlu
s APA15
JTAG Bus I2C Bus
Serial prom 65Kb s
Addres s switche s
ChannelB[7:0 ] Parallel Bus
ds90cv01
RJ4 5
Channel B decode d
resonator
- scillato
r
Cd e & ctrl I/O
JA Connecto r JB Connecto r
I2C/JTAG_DE / 12 I2C / 3 JTAG / 4 I2C_2.5 V
2
I2C_3.3 V
2
I2C/JTAG_RE / 12 I/O / 32
Pro g . Connector.
65Lvds3 2 APA_progra m . / 7
Loc.Addr/ 6
SPECS SLAVE MEZZANINE BOARD
SPEC S SLAV E
PR O
- ASIC3L
JTAG Bus I2C Bus
Serial prom 65Kb s Serial prom 65Kb s
Addres s switche s Addres s switche s
Parallel Bus
ds90cv01 ds90cv01
RJ4 5 resonator
- scillato
r
Cd e & ctrl I/O
JA Connecto r JB Connecto r
I2C/JTAG_DE / 12 SPI JTAG I2C_2.5 V I2C_3.3 V
2
I2C_3.3 V
2
I2C/JTAG_RE / 12 I/O / 32
Pro g . Connector.
65Lvds3 2 65Lvds3 2 APA_progra m . / 7
Loc.Addr/ 6
FPGA FPGA ProASIC3L from ACTEL. ProASIC3L from ACTEL. Triple voting register. Triple voting register. Transfer rate Transfer rate: ~ 14Mbits/s : ~ 14Mbits/s Address: Address: Local address switch. Local address switch. Broadcast address capability. Broadcast address capability. On board clock On board clock: Crystal resonator : Crystal resonator Programmable clock for SPECS read back: Programmable clock for SPECS read back: Long distance capability Long distance capability: 120m cat6 cable : 120m cat6 cable User User Serial EEPROM Serial EEPROM: 65Kbits capacity : 65Kbits capacity JTAG bus, I2C bus, SPI Bus JTAG bus, I2C bus, SPI Bus
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SuperB XTCA – CERN Lyon 0512 D.Charlet
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SPECS slave functions
Features of slave: Features of slave:
- SPECS bus
SPECS bus: : Point to point slave interface Point to point slave interface Multi drop Multi drop
- Parallel interface
Parallel interface: : Parallel bus (16data, 8address) Parallel bus (16data, 8address) 32 configurable I/O lines 32 configurable I/O lines
- Serial interface
Serial interface: : Long distance I2C bus Long distance I2C bus On board I2C bus On board I2C bus JTAG bus JTAG bus 12 receiver enable 12 receiver enable 12 driver enable 12 driver enable
- Interrupt
Interrupt: : User interrupt User interrupt Transmission error Transmission error
- Serial EEPROM interface
Serial EEPROM interface: : Identification register Identification register Users register Users register
Data [15:0] Subadd [7:0]
SDA_MS
Read* Write* User Interrupt
Resonator Ctrl
Reset* Slave Address [5:0]
SCL_MS SDA_SM SCL_SM
SPECS slave
Slave_mode
Reset_out *
On board & chaining SPECS bus Parallel bus Channel B Cde register
Serial prom Access
Global ctrl SPECS identification
SCL_SM spy
Data ready Dtack
TDO TMS TCK TDI
JTAG I2C
I2C long_distance I2C_PROM I2CJTAG_DE[15:0] I2CJTAG_RE[15:0] I2C_3.3v I2CS_DCU SDAIN_board SCLIN_board SDAOUT_board SCLOUT_board SCLSDA_DE
Point to point SPECS bus
I2C_2.5v
Leds Cmd
Clock_out Clock_in
Clock Ctrl Reset Ctrl
Data [15:0] Subadd [7:0]
SDA_MS
Read* Write* User Interrupt
Resonator Ctrl
Reset* Slave Address [5:0]
SCL_MS SDA_SM SCL_SM
SPECS slave
Slave_mode
Reset_out *
On board & chaining SPECS bus Parallel bus Channel B Cde register
Serial prom Access
Global ctrl SPECS identification
SCL_SM spy
Data ready Dtack
TDO TMS TCK TDI
JTAG I2C
I2C long_distance I2C_PROM I2CJTAG_DE[15:0] I2CJTAG_RE[15:0] I2C_3.3v I2CS_DCU SDAIN_board SCLIN_board SDAOUT_board SCLOUT_board SCLSDA_DE
Point to point SPECS bus
I2C_2.5v
Leds Cmd
Clock_out Clock_in
Clock Ctrl Reset Ctrl
SLIDE 15
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Ethernet SPECS master
Cyclone V GX Cyclone V GX
FLASH FLASH DDR3 DDR3 @ @ Data Data MMC MMC Clock out 1 serial link 8 serial links 1 PCIe link 1 GBe link PCIe Clock Clock In
copper Interface copper Interface
serial links
ECS path
AMC connector
X_FPGA p TFC path
Throttle in, out Clock In and out I/O
Mezzanine AMC generic board
SLIDE 16
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ECS xTCA architecture
Cyclone FPGA channels receivers 1 Gigabit Ethernet transceiver
Throttle switch board (AMC generic) NAT MCH (Tongues 1 and 2)
NIOS
Standard backplane (dual star layout)
1 mezzanine board Gigabit Ethernet Switch CPU
Ethernet link
SMA Clock distribution
Tongue 1 Tongue 2 Tongues 3 & 4
External clock Cyclone FPGA channels receivers
SPECS master board (AMC generic)
NIOS 1
mezzanine board Cyclone FPGA channels receivers
SPECS master board (AMC generic)
NIOS 1
mezzanine board
SLIDE 17
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