Wire Shaping is Practical Hongbo Zhang and Martin D.F. Wong, U of - - PowerPoint PPT Presentation

Wire Shaping is Practical

Hongbo Zhang and Martin D.F. Wong, U of Illinois Kai-Yuan (Kevin) Chao, Intel Liang Deng, Broadcom

ISPD-09

Overview

• Practical wire shaping methodology for power

minimization

• Manufacturing for design (MFD)
• Minimal design/manufacturing overhead
• Printability analysis of non-uniform wire shape by

litho simulations

Manufacturing Impact Design

• Manufacturing has inevitable impacts on design

– CMP thickness – Lithography pattern – Dummy fill coupling capacitance

• Circuit properties can be modified during manufacturing

– Poly gate bias for leakage

[ Gupta & Kahng DAC04]

Manufacturing for Design

Performance Power Signal Integrity Yield CD Geometry DFM MFD DESIGN

MANUFACTURING

... ...

Interconnect Power Consumption

• Dynamic power consumption in

interconnect makes up of 53% of the total dynamic power

• The share is increasing
• Reducing dynamic power

consumption is important

[Shekhar Y. Borkar, CRL – Intel] [ Magen, et. al., SLIP04]

• Non-uniform wire shape was studied for delay

minimization (RC depends on wire shape)

• Exponential wire shape has been found to be effective

for delay minimization

• We would like to use non-uniform wire shape to reduce

power

Non-Uniform Wire Shape

x f(x) L CL A+ A-

− + −

= Δ ∝ Δ ∝ Δ A A A C P

• Non-uniform wire shape was considered not practical

– Routing tools can not handle it – Design database becomes too large – DRC issue

Is Non-Uniform Wire Shape Practical?

GDSII:

A Practical Flow with Wire Shaping

Regular Flow

Design Manufacturing GDSII Wire Shaping w/o Changing Delay Design Manufacturing GDSII

Modified Flow

A Practical Flow with Wire Shaping

GDSII*: GDSII with shape annotation Manufacturing*: Minor modification for non- uniform wire shape Wire Shaping w/o Changing Delay Design Manufacturing GDSII Wire Shaping w/o Changing Delay Design Manufacturing* GDSII*

GDSII size explosion!

Manufacturing Non-Uniform Wire

• Current OPC technology can be easily modified to

produce non-uniform wire shape

• OPC edge movement can be targeted for non-uniform

wire shape

• Minimal extra cost

OPC

Edge Segmentation Edge Movement + Optical Simulation Edge Movement + Optical Simulation

Improved Wire Segmentation for OPC

• Minimize number of stages by an improved wire

segmentation scheme

• Can be easily integrated into mainstream OPC tools

• Trade-off between number of segments and error of wire

shape approximation

• Minimize number of segments subject to given error

bound on shape approximation

• Iterative algorithm

– Pick next segmentation point by the equation – Stage length is monotonically increasing

Algorithm for Wire Segmentation

2 1 2

( ) 1 max_ ( ) max ( ) 1

i i i i

f x jog x x f x f x

+

′ + = + ′ ′ +

Exponential Wire Shape

( ) ( ( ) ) ( ( ) ) ( )

L L L d L L x

r D f R C c f x dx c f t dt C dx f x = + + +

∫ ∫ ∫

Delay:

2

( ) ( ( ) )

L L f

• DD

clk

P f C c L c f x dx V f α = + + ∫

Dynamic Power: Minimize s.t. ( ) D f delay =

( ) P f

Problem: Optimal Solution:

( )

bx

f x ae− =

Wire Shape Optimization

Known: min D(f ) f is exponential Our Problem: min P(f ) s.t. D(f ) = delay Equivalent Problem: min P(f ) s.t. D(f ) ≤ delay Can be solved by Lagrangian Relaxation (LR):

• Discrete version: min P(y1, …, yn) s.t. D(y1, …, yn) ≤ delay
• Geometric program Convex Exactly solved by LR
• Fix λ ≥ 0, solve min P(y1, …, yn) + λ(D(y1, …, yn) – delay)
• Updateλand iterate
• Discrete version Continous version as n ∞

Wire Shape Optimization

min P(f ) s.t. D(f ) = delay min P(f ) + λ(D(f ) – delay) min λ D(f ) + constant min D(f ) Exponential Wire Shape!

D(f) is delay with modified driver resistance

• HSPICE
• Constraints:

– Small timing range – Wmax and Wmin – Exponential wire shape

Wire Delay vs Wire Shape

Wire Delay vs. Wire Shape

100um length, 45nm technology Original: 100nm wire width

Optimal Wire Shape

+ =

Power Timing

Intersection Obtain optimal wire shape from a set of wire shape candidates

Exponential vs. Uniform (Ideal)

100nm

50nm

Pitch: 240nm Max: 100nm Min: 45nm

Exponential vs. Uniform (Mask)

Exponential vs. Uniform (Silicon)

Similar Mask Complexity

uniform exponential

Post-OPC GDSII Size Comparison

0X 2X 4X 6X 8X 10X 12X 14X 16X 100nm 80nm 60nm Wire Width Relative Size of PostOPC layout compared to its original PreOPC layout

10 Tracks with Tapered Wire 10 tracks with Uniform Wire 50 tracks with Tapered Wire 50 tracks with Uniform Wire

Accurate Fabrication of Exponential Wire

• 0.43%
• 3.28%

45 67.5 1000

• 0.44%
• 3.17%

45 67.5 750

• 1.22%
• 3.54%

47.5 75 500

• 1.23%
• 0.29%

47.5 70 250

• 0.68%

5.55% 50 65 100

• 0.43%

2.97% 50 60 75

• 0.32%

4.61% 52.5 65 50 Diff in Timing Diff in Capacitance Wsink (nm) Wsource (nm) Wire Length (um)

Intended wire shape vs. simulated wire shape

• Original wire width is 100nm and pitch is 240nm
• Extraction and timing simulation are based on post-OPC simulation
• Timing and area control is accurate

Results on Power Minimization

1% 43.58% 46.22% 45 67.5 1000 1% 42.71% 46.16% 45 67.5 750 2% 37.28% 41.79% 47.5 75 500 1% 33.83% 42.03% 47.5 70 250 2% 24.64% 39.57% 50 65 100 1% 24.04% 43.47% 50 60 75 1% 17.50% 38.71% 52.5 65 50 Delay Variation Saving in Dynamic Power Saving in Capacitance Wsink (nm) Wsource (nm) Wire Length (um)

Power Minimization v.s. Delay Minimization

• Wire Shaping is more effective for power minimization

Power Minimization Delay Minimization

Conclusion

• Presented a wire shaping methodology with minimal

design/manufacturing overhead

• Demonstrated accurate printing of exponential wire

shape by litho simulations

• Obtained substantial reduction of power without

affecting timing closure

• An excellent example of manufacturing-for-design
• Wire shaping is practical