Welcome to 2017 Analyst Day September 21, 2017 Safe Harbor for - - PowerPoint PPT Presentation

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Welcome to 2017 Analyst Day September 21, 2017 Safe Harbor for - - PowerPoint PPT Presentation

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Welcome to 2017 Analyst Day September 21, 2017 Safe Harbor for Forward-Looking Statements This presentation contains forward-looking statements regarding our financial prospects, including financial guidance for 3Q-2017, markets, demand for our

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Welcome to 2017 Analyst Day

September 21, 2017

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This presentation contains forward-looking statements regarding our financial prospects, including financial guidance for 3Q-2017, markets, demand for our products, and product development, among other things. Such forward-looking statements are based on current expectations, estimates and projections about the Company’s industry and management’s beliefs and assumptions. These statements are subject to risks and uncertainties which are more fully described in the documents that we file with the SEC, including our 10-Ks, 10-Qs and 8-Ks, and these statements may differ materially from our actual results. This presentation contains non-GAAP financial measures such as non-GAAP operating Income, margin and EPS, and Adjusted EBITDA and EBITDA margins. We believe the presentation of these non-GAAP measures provide management and investors with meaningful information to understand and analyze our financial

  • performance. Reconciliations of these non-GAAP measures to their most directly comparable GAAP measures

can be found in the Appendix to the presentation. However, this presentation should not be considered in isolation or as a substitute for the comparable GAAP measurements, when available.

Safe Harbor for Forward-Looking Statements

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Data Center

Luc Seraphin

General Manager, Memory & Interfaces Division

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Cores

SerDes PHYs

Move data from chip to chip

Memory PHYs

Move data between chips and memory

Chips

Server DIMM Chipsets

Enables more capacity at high performance

The Data Center

Data・Faster

Data Center

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Building Momentum

Rambus, PLDA and Avery Design Announce Comprehensive PCIe 4.0 Solution Rambus Introduces High Bandwidth Memory PHY on GLOBALFOUNDRIES FX-14™ ASIC Platform using 14nm LPP Process Technology Rambus Partners with Samsung to Develop 56G SerDes PHY on 10nm LPP Process GLOBALFOUNDRIES Demonstrates 2.5D High-Bandwidth Memory Solution for Data Center, Networking, and Cloud Applications Rambus Launches JEDEC-Standard DDR4 NVRCD for Emerging NVDIMM Applications

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Real-time Applications Demand More Memory

Telecom & Cloud

More customer transactions

Business Intelligence

Better insights and more

  • pportunities

Financial Services

Faster transactions and more accurate assessments

Health & Life Sciences

Solve complex problems with better, faster results

High-bandwidth memory capacity is critical for real-time applications

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Exponential data growth is driving performance requirements and new architectures High-speed interconnects are key to data center performance and growth

Exponential Data Growth Mandates Increased Speed

20 40 60 80 100 120 140 160 180 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

Zetabytes

Source: IDC's Data Age 2025 Study

Data Created

Size of Global Data Creation

Cloud Services IoT Devices Streaming Video Social Media eCommerce Wireless Networks Big Data Data Center Servers Storage

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Cores

SerDes PHYs

Move data from chip to chip

Memory PHYs

Move data between chips and memory

Chips

Server DIMM Chipsets

Enables more capacity at high performance

The Data Center

Data・Faster

Data Center

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Rambus High-speed IP Ecosystem

Technology Foundry Design/ Validate IP License IP Direct License IP Sell ASIC Networking Data Center Communications ASIC House/ SOC Integrators

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High-speed Interface IP: The Data Center’s Backbone

Largest data centers require millions of high-speed memory and SerDes cores

  • Large Data Centers exceed 100,000

servers

  • More than a dozen high-speed interfaces

required per server

Exponential growth

  • Total data center market expected to

double in size between 2015 and 2020*

  • Data center cloud usage 30% expected

CAGR through 2020*

*http://www.cisco.com/c/dam/en/us/solutions/collateral/service-provider/global-cloud-index-gci/white-paper-c11-738085.pdf

Typical server line card

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Rising design cost and complexity promotes using proven, high performance margin IP solutions

Source: SEMICO Research IP Integration cost based on node, not date

In-house design cost increasing

  • Approaching ~200 IP blocks per SoC
  • Over $160M in design implementation costs
  • $10M+ potential revenue loss if late to market due

to re-spin Low risk solutions ➡ Reduce time-to-market

  • Validated, tested, and silicon proven
  • Qualified with industry Fab partners
  • Robust and high-margin solutions

More than a PHY vendor

  • History of industry leading memory solutions
  • Integrated customer IP
  • System and packaging design capabilities

SoC Cost and Complexity on the Rise

50 100 150 200 250 50 100 150 200 250

SOC IP Cores and IP Integration Cost Trend

IP Cores per SoC IP Integration Costs in $M

Cores Costs

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Complete Solutions: SerDes PMA+ PCS, MAC (Partners)

Rambus High-Speed SerDes PHY Solutions

Lead Customers

Integrated tools for easy bring-up and characterization Validated solutions with partners

  • PCIe 4/3/2
  • CEI 11/6
  • XFI/XAUI
  • SATA
  • SAS

16G

28nm & 14nm

  • CEI-

28/25/11/6

  • 100/50/25G

bE

  • 10G-KR
  • FC28
  • XFI/XAUI

28G

14nm & 7nm*

  • CEI-56G MR
  • CEI-56G LR
  • CEI-

28/25/11

  • 400GbE
  • PAM-4/NRZ

LEAD CUSTOMERS

56G

10nm

  • 112G Single

Lane

  • CEI-56G MR
  • CEI-56G LR
  • CEI-28/25
  • PAM-4/8

IN DEVELOPMENT

112G

7nm

*In Development

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Integrated tools for easy bring-up and characterization

Rambus Memory PHY Solutions

Lead Customers

  • 3200Mbps
  • x16 –

x72-bits

  • 1-4 Ranks
  • DFI 4.0

DDR4/3

28nm & 14nm

  • 2000Mbps
  • 1024-bit
  • 2.5D design

architecture

HBM2

14nm & 7nm*

  • Expected

4000Mbps

  • Complex

design architectures

IN DEVELOPMENT

HBM3

7nm

  • Expected

4800 – 6400Mbps

IN DEVELOPMENT

DDR5

7nm

Validated solutions with partners

LabStation Platform On-chip Noise Monitor

Memory PHY Solutions for Networking and Data Center

*In Development

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Cores

SerDes PHYs

Move data between chips and memory

Memory PHYs

Move data chip and memory

Chips

Server DIMM Chipsets

Enables more capacity at high performance

The Data Center

Data・Faster

Data Center

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Server DIMM Chipset Ecosystem

DRAM/Module Mfrs Support Services Chip Validation List RDIMMs & LRDIMMs Server DIMM Chipset DIMM Validation Chip/DIMM Validation

Data Center Enterprise

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  • Server DIMM chipsets continue to expand

the potential capacity and performance of DRAM

  • Rambus is also continuously exploring

alternatives to accelerate the delivery and computation of data to close the latency gap between SCM and storage.

Extend and Expand Current Technology’s Range

Processing Memory Storage

CPU

SSD HDD

DRAM NVDIMM SCM

Memory Hierarchy

Size: 1x Latency: 1x Size: 10x Latency: 100x Size: 100x Latency: 1,000x Size: 10,000x Latency: 10,000,000x Size: 100x Latency: 100,000x

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Boost Memory Capacity at Peak Bandwidth

Server DIMM Chipsets enable increased capacity at peak DRAM performance

Registered DIMM (RDIMM) - RCD Load Reduced DIMM (LRDIMM) – RCD + DB Load Reduced NVDIMM (LRDIMM) – NVRCD

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

NVRCD

NVDIMM Controller Persistent Memory

Persistent 12V Power Rail Clock Command/ Address

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

RCD Data Clock Command/ Address

DB DB DB DB DB DB DB DB DB DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

RCD Data Clock Command/ Address

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Smart tools for easy integration and reduced time to market

Rambus Server DIMM Chipset Solutions

Lead Customers

  • JEDEC

compliant

  • Speeds up

to 2133

  • Multiple

OEM qualifications

AVAILABLE IN PRODUCTION

DDR3

DB & RCD

  • JEDEC

compliant

  • Speeds up

to 3200

  • Multiple

OEM qualifications

AVAILABLE IN PRODUCTION

DDR4

DB & RCD

  • JEDEC

compliant

  • Speeds up

to 3200

  • Ongoing

qualifications

AVAILABLE IN PRODUCTION

DDR4

NVRCD

  • Consistent

with JEDEC direction

IN DEVELOPMENT

DDR5

DB & RCD

Validated solutions with partners

LabStation Platform Buffer Bios Integration Tool

Server DIMM Chipsets: Delivering performance and capacity

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Introducing DDR5 Server DIMM Chips

Rambus Announces Industry’s First Functional Silicon of Server DIMM Buffer Chipset Targeted for Next-generation DDR5 Memory Technology

Provides data center architects early path to next-generation memory speeds

SUNNYVALE, Calif. – Sept. 20, 2017 – Rambus Inc. (NASDAQ: RMBS) today announced functional silicon of a double data rate (DDR) server DIMM (dual inline memory module) buffer chip prototype for the next generation DDR5 memory technology. This represents a key milestone for Rambus and the industry’s first silicon-proven memory buffer chip prototype capable of achieving the speeds required for the upcoming DDR5 standard.

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Growing Opportunity in Data Center

$M

Source: IHS, Gartner, Semico Research, and Rambus estimates

200 400 600 800 1,000 1,200 1,400 2016 Rev 2016 SAM 2018 SAM 2021 SAM

Revenue Architecture Licensing and Cores Chips

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