VLSI Testing Power Aware Serial Scan Virendra Singh Associate - - PowerPoint PPT Presentation

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VLSI Testing Power Aware Serial Scan Virendra Singh Associate - - PowerPoint PPT Presentation

VLSI Testing Power Aware Serial Scan Virendra Singh Associate Professor C omputer A rchitecture and D ependable S ystems L ab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail:


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SLIDE 1

CADSL

VLSI Testing

Power Aware Serial Scan

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

EE-709: Testing & Verification of VLSI Circuits

Lecture 25 (21 March 2013)

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SLIDE 2

CADSL

T-Flip-Flop based Scan cell for RAS

To Bus Leading to Primary O/P From Combinational Logic CLK Row Col To combinational Logic

Row Decoder Column Decoder

lines

ff

N

lines

ff

N

2

{log }

ff

Address N

2 EE-709@IITB Feb 28, 2012

Mudlapur, VDAT’05

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SLIDE 3

CADSL

Modified T-Flip-Flip based Cell

CTR CTR CTR

Test Control

Single Ended Read Circuits and MISR

CTR CTR CLK CLK CLK CLK CLK CLK CLK AOI D Q BIT Test Enable CLK READ

Row Decoder Col Decoder Address lines

ff

N lines

ff

N

Architecture Functional Mode Test Application & Simultaneous Read Reading Response

  • nly

1 1 1 RA CA 1 1 3 Feb 28, 2012

Gandhi, ETS’10

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SLIDE 4

CADSL

Critical Path Analysis

To Bus Leading to Primary O/P To combinational Logic From Combinational Logic CLK Row Col CLK D D Q Q CTR CTR

TFF Based Scan Cell MTFF Based Scan Cell

4 EE-709@IITB Feb 28, 2012

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SLIDE 5

CADSL

Gate Overhead

Circuit #FF #Gates GOV_SS GOVTFF_ RAS GOVMTFF _RAS S5378 179 2779 17.47% 25.3% 20.3% S9234 228 5597 12.04% 17.44% 13.99% S13207 669 7951 21.36% 30.75% 24.6% S15850 597 9772 16.7% 24.15% 19.36% S35932 1728 16065 25.36% 36.4% 29.1% S38417 1636 22179 19.3% 27.8% 22.2% S38584 1452 19253 19.7% 28.3% 22.6%

5 EE-709@IITB Feb 28, 2012

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SLIDE 6

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Efficient Decoder Design

Optimize the column decoder Uses concept of basis vectors in linear algebra Minimizes the number of linear combinations of basis vectors to generate the transition vectors Directly related to the no. of clock cycles 2-3 times speed up compare to standard RAS

Feb 28, 2012 EE-709@IITB 6

Abhishek, ISCAS’10

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SLIDE 7

CADSL

Should Serial Scan Continue?

  • Three Problems with serial-scan

– Test power – Test application time – Test data volume

  • Efforts and limitations

– ATPG for low test power consumption  Test power  Test length  – Reducing scan clock frequency  Test power  Test application time  – Scan-chain re-ordering (with additional logic insertion)  Test power/time  Design time  – Test Compression Test time/data size  Has limited capability for Compacted test

  • Orthogonal attack

– Random access scan instead of Serial-scan – Hardware overhead? Silicon cost << Testing cost

18 Mar 2013 EE-709@IITB 7

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SLIDE 8

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Introduction

sff1 sff2 sff3 sff4 sff5 Combinational Block

PI PO Shift Cycle Capture Cycle 8

21 Mar 2013 EE-709@IITB

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SLIDE 9

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sff1 sff2 sff3 sff4 sff5 Combinational Block

PI PO 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 Initial State Shift Cycle 0 1 1 0 0 Capture Cycle Responses 9

21 Mar 2013 EE-709@IITB

Introduction

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SLIDE 10

CADSL

Introduction

Shift Cycle Capture Cycle Shift & Launch Why ?

  • Why, When & How to reduce power during Scan Testing

➔Peak Power -- Causes IR-Drop, Cross talk. ➔Average Power -- Causes excess heat dissipation.

When ? 10

21 Mar 2013 EE-709@IITB

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SLIDE 11

CADSL

Introduction

How ? Test Pattern Pi Response Ri 1 X 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 1 P1 P2 R1 R2 P2 1 0 1 0 1 0 1 0 1 0 1 1 R1

➔Reduce Intra Pattern Transition ➔Reduce Inter Pattern Transition

1 X 1 0 0 1 P1 X 1 11

21 Mar 2013 EE-709@IITB

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SLIDE 12

CADSL

Problem Statement : Determination of the minimum achievable peak power during test for a given test set and find out a test vector sequence which can support the minimum achievable peak power.

Problem Formulation

21 Mar 2013 EE-709@IITB

Jaynarayan Tudu [ETS 2009]

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SLIDE 13

CADSL

  • Peak power computation:

1 1

Problem Formulation

Next bit to shifted in Test Pattern Pi Response Ri 1 0 1 0 0, 1 0 1 0 1 1 0 1 0 0, 1 0 1 1 0 P1 P2 R1 R2 Computed Transition P2 1 1 1 1 1 0 1 0 3 0 1 1 0 1 4 1 0 1 1 0 4 0 1 0 1 1 4 1 0 1 0 1 4 Peak Power = Max V (total transition per clock) = 4

clock

13

21 Mar 2013 EE-709@IITB

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SLIDE 14

CADSL

Graph theoretic problem formulation

Problem Formulation

P1 P2

Wij = Edge weight = Peak Power = MaxV (total transition per clock)

clock

W12 = 4

V1 V2

Direction of edge is mapped from the order of applying the test vectors Nodes are mapped from corresponding test vector

Vi

A Complete directed weighted graph can be formed by applying test vectors in all possible way 14

21 Mar 2013 EE-709@IITB

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SLIDE 15

CADSL

Problem Formulation

Formulation of Problem1 (Minimal Test time) Given a complete weighted directed graph Dc, find out a Hamiltonian path which has minimum Path- weight which will be the minimum possible peak power Pth1 under minimal test time Problem Statement: Path-weight is defined as the maximum of weight of each edge in the path in a digraph Definition: Example:

V4 V2 V3 V5

3 8 10 10

path-weight = 10 15

V6

7 V1

21 Mar 2013 EE-709@IITB

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SLIDE 16

CADSL

Problem Formulation

Observation:

V0 V1

V2 V3 V4

7 12 7 8

Can we reduce peak power below Pth1 ?

V5 V6

9 10 6 5

Pth1 = 12

V0 V1 V2 V3 V4

7 12 7 8

V5 V6

9 10 6 5

16

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SLIDE 17

CADSL

Problem Formulation

Observation: There can be a walk which visits every node at least

  • nce having walk-weight less than Pth1

Definition : walk-weight is defined as the maximum edge-weight in a walk

V0 V1 V2 V3 V4

7 12 7 8

walk-weight = 10 Can we reduce peak power below Pth1 ?

V5 V6

9 10 6 5

Conclusion:

17

21 Mar 2013 EE-709@IITB

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SLIDE 18

CADSL

Problem Formulation

Formulation of Problem2 (Reapplication of vectors) Given an weighted directed graph D, find out a walk which visits each and every nodes at least once and having minimum walk-weight which corresponds to the peak power Pth2 Problem Statement: Definition: A walk in D is a non-empty alternating sequence of vertices and edges in D 18

21 Mar 2013 EE-709@IITB

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SLIDE 19

CADSL

Problem Formulation

How to reduce further below the Pth2 ? Observation:

V0 V1 V2 V3 V4

7 12 7 8

V5 V6

9 10 6 5

Pth2 = 10

V0 V1 V2 V3 V4

7 7 8

V5 V6

9 6 5

Maximum edge-weight = 9

➔ Further reduction will cause a graph to be disconnected

19

21 Mar 2013 EE-709@IITB

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SLIDE 20

CADSL

Problem Formulation

How to reduce further below the Pth2 ? Observation:

V0 V1 V2 V3 V4

7 7 8

V5 V6

9 6 5

Maximum edge-weight = 9

V0 V1 V2 V3 V4

7 8

V5 V6

9 6 5

Finding out disjoint paths Path 1 Path 2 20

21 Mar 2013 EE-709@IITB

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SLIDE 21

CADSL

Problem Formulation

Formulation of Problem3 (Insertion of new vectors) Problem Statement: Find out a path cover for a given directed graph D and join those disjoint paths of path cover in such a way that a complete walk containing all the vertices can be formed which have minimum possible walk-weight less than Pth2. Definition: A path cover of a directed graph D is a set of disjoint paths in D which together contain all the vertices of D 21

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CADSL

Algorithms

Algorithm1 Objective:

To find out a hamiltonian path which has minimum Path- weight which will be the minimum possible peak power Pth1 under minimal test time for a given complete weighted directed graph Dc,

Working principle: Algorithm1 first transform the weighted complete graph into unweighted graph and then it find out the hamiltonian path on unweighted graph which assure the minimum peak power Pth1. 22

21 Mar 2013 EE-709@IITB

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SLIDE 23

CADSL

Algorithms

Example: P1 P2 P3 P4 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 R1 R2 R3 R4 1 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0

Di V1 V2 V3 V4

7

14 12 7 12 10 8 8 6 7 7 6 5 3

11 8 23

Do 6 10 10 7 5

21 Mar 2013 EE-709@IITB

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SLIDE 24

CADSL

Algorithms

Let following be given complete digraph Step1: Sort the edges in increasing order. Sorted order of edge weight will be: 3,5,6,7,8,10,11,12,14 24

Di V1 V2 V3 V4

7

14 12 7 12 10 8 8 6 7 7 6 5 3

11 8

Do 6 10 10 7 5

21 Mar 2013 EE-709@IITB

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SLIDE 25

CADSL

Algorithms

Removing the edges whose weight is greater than next-weight to transform the given complete weighted graph into unweighted graph. Step2: next-weight=8 is chosen using binary search from sorted edge array 3,5,6,7,8,10,11,12,14 25

Di V 1 V 2 V 3 V 4

7

14 12 7 12 10 8 8 6 7 7 6 5 3

11 8

D

  • 6

10 10 7 5 Di V 1 V 2 V 3 V 4

7

7 8 8 6 7 7 6 5 3

8

D

  • 6

7 5

=>

21 Mar 2013 EE-709@IITB

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SLIDE 26

CADSL

Algorithms

Attempt to find out Hamiltonian path. If path exist then store the path and next-weight value in temp_path and temp_weight and modify the next-weight from left half of array otherwise from right half of array. Go back to Step2. Step3: next-weight=11 => 3,5,6,7,8,10,11,12,14 No Hamiltonian path exist 26

Di V 1 V 2 V 3 V 4

7

7 8 8 6 7 7 6 5 3

8

D

  • 6

7 5 Di V 1 V 2 V 3 V 4 D

  • 21 Mar 2013

EE-709@IITB

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SLIDE 27

CADSL

Algorithms

Removing the edges whose weight is greater than next-weight to transform the given complete weighted graph into unweighted graph. Step2: next-weight=11 => 3,5,6,7,8,10,11,12,14 Sorted edge array: 27

Di V 1 V 2 V 3 V 4

7

14 12 7 12 10 8 8 6 7 7 6 5 3

11 8

D

  • 6

10 10 7 5 Di V 1 V 2 V 3 V 4

7

7 10 8 8 6 7 7 6 5 3

11 8

D

  • 6

10 10 7 5

21 Mar 2013 EE-709@IITB

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SLIDE 28

CADSL

Algorithms

Attempt to find out Hamiltonian path. If path exist then store the path and next-weight value in temp_path and temp_weight and modify the next-weight from left half of array otherwise from right half of array. Go back to Step2. Step3: next-weight=10 => 3,5,6,7,8,10,11,12,14 Hamiltonian path exist 28

Di V 1 V 2 V 3 V 4

7

7 10 8 8 6 7 7 6 5 3

11 8

D

  • 6

10 10 7 5 Di V 1 V 2 V 3 V 4 D

  • 21 Mar 2013

EE-709@IITB

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SLIDE 29

CADSL

Algorithms

Removing the edges whose weight is greater than next-weight to transform the given complete weighted graph into unweighted graph. Step2: next-weight=10 => 3,5,6,7,8,10,11,12,14 Sorted edge array: 29

Di V 1 V 2 V 3 V 4

7

14 12 7 12 10 8 8 6 7 7 6 5 3

11 8

D

  • 6

10 10 7 5 Di V 1 V 2 V 3 V 4

7

7 10 8 8 6 7 7 6 5 3

8

D

  • 6

10 10 7 5

21 Mar 2013 EE-709@IITB

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SLIDE 30

CADSL

Algorithms

Attempt to find out Hamiltonian path. If a path exists then store the path and next-weight value in temp_path and temp_weight and modify the next-weight from left half of array otherwise from right half of array. Go back to Step2. Step3: => 3,5,6,7,8,10,11,12,14 Hamiltonian path found and Binary search process exhausted, hence algorithm will stop here. 30

Di V 1 V 2 V 3 V 4

7

7 10 8 8 6 7 7 6 5 3

8

D

  • 6

10 10 7 5 Di V 1 V 2 V 3 V 4 D

  • 21 Mar 2013

EE-709@IITB

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SLIDE 31

CADSL

Algorithms

Hamiltonian path found is:

Pth1 = 10

31

Di V 1 V 2 V 3 V 4 7 8

8

D

  • 10

5

And corresponding peak power is:

21 Mar 2013 EE-709@IITB

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SLIDE 32

CADSL

Algorithms

Algorithm2 Objective: Working principle: Algorithm2 first transform the weighted complete graph into unweighted graph and then it find out the walk on unweighted graph which assure the minimum peak power Pth2. Find out a walk which visits each and every nodes at least once and having minimum walk-weight which corresponds to the peak power Pth2, for a given weighted directed graph D, 32

21 Mar 2013 EE-709@IITB

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SLIDE 33

CADSL

Algorithms

Let following be given complete digraph: Step1: Given a sorted edge weights : 3,5,6,7,8,10,11,12,14. 33 Let Pthtemp = Pth1= 10

Di V 1 V 2 V 3 V 4

7

14 12 7 12 10 8 8 6 7 7 6 5 3

11 8

D

  • 6

10 10 7 5

21 Mar 2013 EE-709@IITB

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SLIDE 34

CADSL

Algorithms

Remove the edges whose weight is greater than or equal to

Pthtemp to transform the given complete weighted graph into

unweighted graph Du. Step2:

Note: Rest of the work onwards will be done in unweighted graph only

=> Pthtemp=10 34

Di V 1 V 2 V 3 V 4

7

14 12 7 12 10 8 8 6 7 7 6 5 3

11 8

D

  • 6

10 10 7 5 Di V 1 V 2 V 3 V 4

7

7 8 8 6 7 7 6 5 3

8

D

  • 6

7 5

21 Mar 2013 EE-709@IITB

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SLIDE 35

CADSL

Algorithms

Step3 : Find out the walk in unweighted graph Du: Transform the unweighted graph Du into directed acyclic graph(DAG) by forming each cycle present in Du in to corresponding supernode 35

D i V 1 V 2 V 3 V 4 D

  • Di

V 1 V 2 V43 D

  • D

i V 1 V432 D

  • 21 Mar 2013

EE-709@IITB

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SLIDE 36

CADSL

Algorithms

Find out a hamiltonian path in the DAG. If path exist store it in HAMtemp and assign Pthtemp= NextSmallEdgeWeight and goto Step2 else goto next step NextSmallEdgeWeight=8 Go to Step2... Given sorted array of edge weight: 3,5,6,7,8,10,11,12,14. 36

D i V 1 V432 D

  • D

i V 1 V432 D

  • =>

21 Mar 2013 EE-709@IITB

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SLIDE 37

CADSL

Algorithms

Go to next step... 37 Step 2 is repeated for edge-weight = 8. For this running example path does not exist for edge-weight=8

21 Mar 2013 EE-709@IITB

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SLIDE 38

CADSL

Algorithms

Go to next step... If HAMtemp is empty then Print “no path below Pth1” else goto next step HAMtemp in running example is : 38

D i V 1 V432 D

  • 21 Mar 2013

EE-709@IITB

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SLIDE 39

CADSL

Algorithms

Form a final walk by unrolling (expanding) each of the supernode

Di V2 V4 V3 V4 V1

7 8 6 7 8 Hence the path given by Algo2 is:

Pth2 = 8 < Pth1=10

39

Di V 1 V432 D

  • Di

V4 V1 V 2 V3 V4 Do

=>

D

  • 7

21 Mar 2013 EE-709@IITB

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SLIDE 40

CADSL

Algorithms

Find out a path cover for a given directed graph D and join those disconnected paths of path cover in such a way that a complete walk containing all the vertices can be formed which has minimum possible walk-weight correspond to Pth3 less than Pth2. Objective: Algorithm3 Working principle: Algorithm3 first transform the weighted complete graph into unweighted graph and then it find out the walk on unweighted graph which assure the minimum peak power Pth3. 40

21 Mar 2013 EE-709@IITB

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SLIDE 41

CADSL

Algorithms

Remove the edges having weight ≥ Pthtemp to transform the given complete weighted graph into unweighted graph Du. Given a sorted edge-weight: 3,5,6,7,8,10,11,12,14. Let Pthtemp = Pth2= 8 41

Di V 1 V 2 V 3 V 4

7

14 12 7 12 10 8 8 6 7 7 6 5 3

11 8

D

  • 6

10 10 7 5 Di V 1 V 2 V 3 V 4

7

7 6 7 6 5 3 D

  • 6

7 5

21 Mar 2013 EE-709@IITB

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SLIDE 42

CADSL

Algorithms

Find a path cover in the unweighted graph Du 42

Di V 1 V 2 V 3 V 4 D

  • Di

V 1 V 2 V 3 V 4 D

  • Path cover

21 Mar 2013 EE-709@IITB

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SLIDE 43

CADSL

Algorithms

Pth3 =6 < Pth2 = 8 < Pth1=10

43 Connect each paths to form a walk using node Va0 and Va1

Di V1 V 2 V 3 V 4 D

  • Va

1 Va 1

21 Mar 2013 EE-709@IITB

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SLIDE 44

CADSL

Algorithms

Summary:

Pth3 =6 < Pth2 = 8 < Pth1=10

Algorithm1 without increasing test time Algorithm2 by revisiting of some nodes with increase in certain amount of test time Algorithm3 by introduction of two new nodes with increase in certain amount of test time

Can peak power be reduced further ?

44

21 Mar 2013 EE-709@IITB

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CADSL

Lower bound on Minimum Peak Power

45

Di V 1 V 2 V 3 V 4

7

14 12 7 12 10 8 8 6 7 7 6 5 3

11 8

D

  • 6

10 10 7 5 Di V 1 V 2 V 3 V 4 D

  • Va

Va 1

Maximum allowed test time:

21 Mar 2013 EE-709@IITB

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SLIDE 46

CADSL

Theorem 1: The minimum achievable peak power for a test set is , Max i [Max{Min(EWa0i , EWa1i), Min(EWia0, EWia1)}] Lemma 1 : Let there be a test set of n vectors, and scan chain length be l. The worst case test time to achieve the minimum bound is (n – 1)(l + 1)+2(n-1)*l + l

Lower bound on Minimum Peak Power

Di Vi Vj Vk D

  • Va

Va

1

Va

1

Va Va Va

1

46

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CADSL

Lower bound on Minimum Peak Power

47

Di V 1 V 2 V 3 V 4 D

  • Va

Va 1 Di V 1 V 2 V 3 V 4 D

  • Va

Va 1

Reduced test time:

21 Mar 2013 EE-709@IITB

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SLIDE 48

CADSL

Corollary 1 : The minimum achievable peak power under maximum test time (2n – 1) (l+1) + (n-1) * l + l is Max i [Max(EWa0i , EWa1i , EWia0, EWia1)]

Lower bound on Minimum Peak Power

V0 Vi Vj Vk Vn Va Va

1

Va

1

48

21 Mar 2013 EE-709@IITB

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SLIDE 49

CADSL

Experimental Results

b14 b22 s1196 s838 b07 s38417 s13207 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35

Comparision of Results

Algo 1 Algo 2 Algo 3 Lower bound

Benchmark Cicuits % of reduction over random order

49

21 Mar 2013 EE-709@IITB