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Using CPAL to model and validate the timing behaviour of embedded - - PowerPoint PPT Presentation

Using CPAL to model and validate the timing behaviour of embedded systems Sebastian Altmeyer, Nicolas Navet, Lo c Fejoz FMTV Challenge - WATERS 2015 - Lund Cyber Physical Action Language (CPAL) C-like intuitive language (with automata


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Using CPAL to model and validate the timing behaviour of embedded systems

Sebastian Altmeyer, Nicolas Navet, Lo¨ ıc Fejoz

FMTV Challenge - WATERS 2015 - Lund

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Cyber Physical Action Language (CPAL)

◮ C-like intuitive language (with automata and real-time

abstractions)

◮ model functional and temporal behaviour of CPS ◮ simulate CPS (both types of behaviour)

(still under development)

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The challenging part of the challenge

◮ not a standard scheduling problem ◮ hidden ambiguity in the model ◮ pen & paper solutions seemed trivial

How to solve the challenge with CPAL

◮ low effort to model the challenge ◮ quick simulation results ◮ explicit dis-ambiguity

(yet, simulation formal verification)

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CPAL Model of Challenge 1

struct Frame { uint32: id; uint32: emission_time; }; processdef T1_PreProcessor( in channel<Frame>: input,

  • ut channel<Frame>: output)

{ state Main { /* removes reflections normalizes intensity, etc. */ assert(input.notEmpty());

  • utput.push(input.pop());

} } var queue<Frame>: cam_to_t1[1]; var queue<Frame>: t1_to_t2[1]; var Frame: t2_to_t3; var queue<Frame>: t3_to_t4[n]; var queue<Frame>: t4_to_monitor[1]; process T1_PreProcessor: t1[cam_to_t1.notEmpty()](cam_to_t1, t1_to_t2); @cpal:time { t1.execution_time = 28ms; } ... 3 / 11

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Explicit Disambiguation

◮ task release times ◮ mutable or immutable clock drifts ◮ clock drift distribution ◮ execution time distribution

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always the least-favorable configuration chosen

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Simulation of Challenge 1A

n = 1

0.005 0.01 0.015 0.02 0.025 0.03 8 9 1 1 1 1 2 1 3 1 4 1 5 Frequency Latency

n = 3

0.005 0.01 0.015 0.02 0.025 8 1 1 2 1 4 1 6 1 8 2 2 2 Frequency Latency

◮ 108 frames in total simulated (in less than 8 hours) ◮ 103 release patterns, 105 frames per pattern ◮ mutable drifts ◮ normal distributions

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Simulation vs. Pen & Paper

buffer (n) frame simulation pen & paper min 1 1 63 ms 63 ms 1

> 1

89.7694 ms 89.6656 ms 3 1 63 ms 63 ms 3

> 1

90.0226 ms 89.6656 ms max 1

  • 144.9224 ms

< 146 ms

3

  • 222.9026 ms

< 226 ms

Error in first pen & paper solution identified using simulation

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Simulation of Challenge 1B

n = 1

0.05 0.1 0.15 0.2 1 2 3 4 5 Frequency number of frames between two discarded frames

n = 3

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 3 3 5 4 4 5 5 5 5 6 Frequency number of frames between two discarded frames

◮ 108 frames in total simulated (in less than 8 hours) ◮ 103 release patterns, 105 frames per pattern ◮ immutable drifts, worst-case clock drifts ◮ normal distribution of exec time

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Simulation of Challenge 1B: Observations

n = 1

0.05 0.1 0.15 0.2 1 2 3 4 5 Frequency number of frames between two discarded frames

◮ minimal distance: 2 ◮ overload situations ◮ lost frames very frequent

n = 3

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 3 3 5 4 4 5 5 5 5 6 Frequency number of frames between two discarded frames

◮ minimal distance > 3800 ◮ no bursts ◮ two spikes

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No pen & paper solution to 1B.

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CPAL Model of Challenge 2

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Simulation of Challenge 2

◮ CPAL simulation does not yet support pre-emption ◮ taskset T5, T6, T7 mutually non-pre-emptive

(simulation possible)

◮ taskset T5, T6, T7 treated as artificial task Tx: ◮ ⇒ reduction to standard response-time analysis!

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Conclusions

CPAL doesn’t offer automated formal verification, but:

◮ intuitive modelling (< 4 hours for the both challenges) ◮ quick simulation (< 8 hours for all simulations) ◮ unambiguous description

Integration with formal verification tool future work.