unit 12 modeling timing constraints
play

Unit-12: Modeling timing constraints B. Srivathsan Chennai - PowerPoint PPT Presentation

Dec 29, 2023 •810 likes •1.37k views

Unit-12: Modeling timing constraints B. Srivathsan Chennai Mathematical Institute NPTEL-course July - November 2015 1 / 20 Traffic lights controller Flight control Automatic gear control Pacemaker ATM Controllers need to adhere to strict

  1. Unit-12: Modeling timing constraints B. Srivathsan Chennai Mathematical Institute NPTEL-course July - November 2015 1 / 20

  2. Traffic lights controller Flight control Automatic gear control Pacemaker ATM Controllers need to adhere to strict timing constraints 2 / 20

  3. Traffic lights controller Flight control Automatic gear control Pacemaker ATM eg. when request for gear change is made, response should be within 1s Controllers need to adhere to strict timing constraints 2 / 20

  4. How do we model-check systems with timing constraints? 3 / 20

  5. Adding time to transition systems 4 / 20

  6. Example 1 5 / 20

  7. T RAIN G ATE 6 / 20

  8. T RAIN G ATE approach up near 0 far approach raise 1 3 raise lower enter exit lower exit in 2 down Train Controller Gate 6 / 20

  9. approach up near 0 far approach raise 1 3 raise lower enter exit lower exit 2 in down Train Controller Gate far, 0, up approach Train || Controller || Gate near, 1, up enter lower in, 1, up raise near, 2, down lower enter in, 2, down exit far, 3, down 7 / 20

  10. approach up near 0 far approach raise 1 3 raise lower enter exit lower exit 2 in down Train Controller Gate far, 0, up approach Train || Controller || Gate near, 1, up enter lower in, 1, up raise near, 2, down lower enter in, 2, down exit far, 3, down Unsafe state: Train is in when gate is still up 7 / 20

  11. approach up near 0 far approach raise 1 3 raise lower enter exit lower exit 2 in down Train Controller Gate far, 0, up approach Train || Controller || Gate near, 1, up enter lower in, 1, up raise near, 2, down lower enter in, 2, down exit far, 3, down Unsafe state: Train is in when gate is still up - need to add timing information in the model 7 / 20

  12. T RAIN G ATE approach up near 0 far approach raise 1 3 raise lower enter exit lower exit in 2 down Train Controller Gate < = 1 minute after > 2 minutes after = 1 minute execution time 8 / 20

  13. Coming next: Timed transition systems 9 / 20

  14. approach up near far 0 approach raise enter 1 3 raise lower exit exit lower 2 in down Train Controller Gate 10 / 20

  15. x := 0 approach up near far 0 approach raise enter 1 3 raise lower exit x ≥ 2 exit lower 2 in down Train Controller Gate 10 / 20

  16. x := 0 approach near up far 0 x ≤ 5 approach raise enter 1 3 raise lower exit x ≥ 2 exit lower in 2 in down x ≤ 5 Train Controller Gate 10 / 20

  17. x := 0 approach near up far y := 0 0 x ≤ 5 approach raise enter 1 3 raise lower exit x ≥ 2 exit lower in y == 1 2 in down x ≤ 5 Train Controller Gate 10 / 20

  18. x := 0 approach near up far y := 0 0 y == 1 x ≤ 5 approach raise enter 1 3 raise lower exit x ≥ 2 exit lower in y == 1 y := 0 2 in down x ≤ 5 Train Controller Gate 10 / 20

  19. x := 0 approach lower near comingdown up far y := 0 0 y == 1 x ≤ 5 approach raise enter 1 3 exit x ≥ 2 exit lower in comingup y == 1 y := 0 2 in down x ≤ 5 raise Train Controller Gate 10 / 20

  20. x := 0 z := 0 approach lower near comingdown up far y := 0 0 y == 1 z ≤ 1 x ≤ 5 approach raise enter 1 3 exit x ≥ 2 exit lower in comingup y == 1 y := 0 2 in down x ≤ 5 z ≤ 1 raise z := 0 Train Controller Gate 10 / 20

  21. Reset Invariant Guard x := 0 z := 0 approach lower near comingdown up far y := 0 0 y == 1 z ≤ 1 x ≤ 5 approach raise enter 1 3 exit x ≥ 2 exit lower in comingup y == 1 y := 0 2 in down x ≤ 5 z ≤ 1 raise z := 0 Train Controller Gate 10 / 20

  22. Reset Invariant Guard x := 0 z := 0 approach lower near comingdown up far y := 0 0 y == 1 z ≤ 1 x ≤ 5 approach raise enter 1 3 exit x ≥ 2 exit lower in comingup y == 1 y := 0 2 in down x ≤ 5 z ≤ 1 raise z := 0 Train Controller Gate Train || Gate || Controller 10 / 20

  23. Reset Invariant Guard x := 0 z := 0 approach lower near comingdown up far y := 0 0 y == 1 z ≤ 1 x ≤ 5 approach raise enter 1 3 exit x ≥ 2 exit lower in comingup y == 1 y := 0 2 in down x ≤ 5 z ≤ 1 raise z := 0 Train Controller Gate Train || Gate || Controller Synchronous product gives timed transition system for the joint behaviour 10 / 20

  24. Timed transition system Transition system + Clocks ◮ Resets: to start measuring time ◮ Guards: to impose time constraint on action ◮ Invariants: to limit time spent in a state 11 / 20

  25. UPPAAL - Model-checker for timed transition systems Kim Larsen, Paul Pettersson, Wang Yi - Computer-Aided Verification Award in 2013 for UPPAAL www.uppaal.com 12 / 20

  26. UPPAAL demo 13 / 20

  27. UPPAAL demo ◮ Adding states, transitions and clocks ◮ Simulation environment ◮ (Subset of) CTL property verification 13 / 20

  28. Example 2 14 / 20

  29. p 1 p 3 x y p 2 15 / 20

  30. [ 1, 3 ] p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] 15 / 20

  31. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] 15 / 20

  32. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  33. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  34. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] S: Stable (matches truth table) U: Unstable ( does not match truth table) x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  35. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] S: Stable (matches truth table) U: Unstable ( does not match truth table) S x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  36. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] S: Stable (matches truth table) U: Unstable ( does not match truth table) S U x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  37. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] S: Stable (matches truth table) U: Unstable ( does not match truth table) S U S x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  38. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] S: Stable (matches truth table) U: Unstable ( does not match truth table) S U S U x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  39. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] S: Stable (matches truth table) U: Unstable ( does not match truth table) S U S U S x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  40. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] S: Stable (matches truth table) U: Unstable ( does not match truth table) S U S U S U x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  41. [ 1, 3 ] Inertial delay p 1 [ 1, 2 ] p 3 x y p 2 [ 1, 3 ] [ 1,3 ] S: Stable (matches truth table) U: Unstable ( does not match truth table) S U S U S U S x p 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 / 20

  42. p 1 x 〈 x , p 1 〉 16 / 20

  43. p 1 x 〈 x , p 1 〉 〈 0,1 〉 〈 1,1 〉 〈 1,0 〉 〈 0,0 〉 16 / 20

  44. p 1 x 〈 x , p 1 〉 〈 0,1 〉 〈 1,1 〉 〈 1,0 〉 〈 0,0 〉 16 / 20

  45. p 1 x 〈 x , p 1 〉 x : 1, z 1 := 0 〈 0,1 〉 〈 1,1 〉 〈 1,0 〉 〈 0,0 〉 16 / 20

  46. p 1 x 〈 x , p 1 〉 x : 1, z 1 := 0 〈 0,1 〉 〈 1,1 〉 p 1 : 0, 1 ≤ z 1 ≤ 3 〈 1,0 〉 〈 0,0 〉 16 / 20

  47. p 1 x 〈 x , p 1 〉 x : 1, z 1 := 0 〈 0,1 〉 〈 1,1 〉 x : 0, z 1 ≤ 3 p 1 : 0, 1 ≤ z 1 ≤ 3 〈 1,0 〉 〈 0,0 〉 16 / 20

  48. p 1 x 〈 x , p 1 〉 x : 1, z 1 := 0 〈 0,1 〉 〈 1,1 〉 x : 0, z 1 ≤ 3 p 1 : 0, 1 ≤ z 1 ≤ 3 〈 1,0 〉 〈 0,0 〉 x : 0, z 1 := 0 16 / 20

  49. p 1 x 〈 x , p 1 〉 x : 1, z 1 := 0 〈 0,1 〉 〈 1,1 〉 x : 0, z 1 ≤ 3 p 1 : 1, 1 ≤ z 1 ≤ 3 p 1 : 0, 1 ≤ z 1 ≤ 3 〈 1,0 〉 〈 0,0 〉 x : 0, z 1 := 0 16 / 20

  50. p 1 x 〈 x , p 1 〉 x : 1, z 1 := 0 〈 0,1 〉 〈 1,1 〉 x : 0, z 1 ≤ 3 p 1 : 1, 1 ≤ z 1 ≤ 3 p 1 : 0, 1 ≤ z 1 ≤ 3 x : 1, z 1 ≤ 3 〈 1,0 〉 〈 0,0 〉 x : 0, z 1 := 0 16 / 20

  51. x p 2 y p y 〈 x , y , p 2 〉 〈 000 〉 y : 1 x : 1 y : 0 x : 0 〈 010 〉 〈 100 〉 x : 0, z 2 ≤ 3 y : 0, z 2 ≤ 3 x : 1, z 2 := 0 y : 1, z 2 := 0 p 2 : 0 〈 110 〉 p 2 : 0 p 2 : 1 1 ≤ z 2 ≤ 3 1 ≤ z 2 ≤ 3 1 ≤ z 2 ≤ 3 x : 0, z 2 := 0 y : 0, z 2 := 0 〈 011 〉 〈 111 〉 〈 101 〉 x : 1, z 2 ≤ 3 y : 1, z 2 ≤ 3 17 / 20

  52. [ ] p 1 p 3 p 2 〈 p 1 , p 2 , p 3 〉 〈 001 〉 p 2 : 1 p 1 : 1 p 2 : 0 p 1 : 0 〈 011 〉 〈 101 〉 p 1 : 0, z 3 ≤ 2 p 2 : 0, z 3 ≤ 2 p 1 : 1, z 3 := 0 p 2 : 1, z 3 := 0 p 3 : 1 〈 111 〉 p 3 : 1 p 3 : 0 1 ≤ z 3 ≤ 2 1 ≤ z 3 ≤ 2 1 ≤ z 3 ≤ 2 p 1 : 0, z 3 := 0 p 2 : 0, z 3 := 0 〈 010 〉 〈 110 〉 〈 100 〉 p 1 : 1, z 3 ≤ 2 p 2 : 1, z 3 ≤ 2 18 / 20

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend

Top 5 Timing Closure Techniques Greg Daughtry Correct Timing Constraints Analyze Before

Top 5 Timing Closure Techniques Greg Daughtry Correct Timing Constraints Analyze Before

Top 5 Timing Closure Techniques Greg Daughtry Correct Timing Constraints Analyze Before Doing Implementation Strategies and Directives Congestion and Complexity Advanced Physical Optimization Create Good Timing Constraints

658 views • 31 slides
1 Clock skew optimization Another approach for sequential timing optimization

1 Clock skew optimization Another approach for sequential timing optimization

Sequential Timing Optimization Long path timing constraints Data must not reach destination FF too late d max (i,j) s i + d(i,j) + T setup s j + P i j s s i i sj d(i,j) T setup Short path timing constraints FF should not

85 views • 7 slides
A Highly Compressed Timing Macro-modeling Algorithm for Hierarchical and Incremental Timing

A Highly Compressed Timing Macro-modeling Algorithm for Hierarchical and Incremental Timing

A Highly Compressed Timing Macro-modeling Algorithm for Hierarchical and Incremental Timing Analysis Tin-Yin Lai, and Martin D. F. Wong March. 16, 2018 Outline Introduction Timing Macro-modeling Problem Formulation Previous

397 views • 23 slides
FORMAL MODELING AND VERIFICATION FOR TIMING PREDICTABILITY Mathieu Jan, Mihail Asavoae, Belgacem

FORMAL MODELING AND VERIFICATION FOR TIMING PREDICTABILITY Mathieu Jan, Mihail Asavoae, Belgacem

FORMAL MODELING AND VERIFICATION FOR TIMING PREDICTABILITY Mathieu Jan, Mihail Asavoae, Belgacem Ben Hedia ERTS 2020 Toulouse Outline of the talk Motivations and goals Timing anomalies in Worst-Case Timing Reasoning An example of a timing

286 views • 16 slides
Modeling and Solving Constraints Erin Catto Blizzard Entertainment Basic Idea Constraints

Modeling and Solving Constraints Erin Catto Blizzard Entertainment Basic Idea Constraints

Modeling and Solving Constraints Erin Catto Blizzard Entertainment Basic Idea Constraints are used to simulate joints, contact, and collision. We need to solve the constraints to stack boxes and to keep ragdoll limbs attached.

1.34k views • 81 slides
Accommodations For Students With An IEP or 504 Plan &amp; How To Help Your Child February 1 ,

Accommodations For Students With An IEP or 504 Plan &amp; How To Help Your Child February 1 ,

Accommodations For Students With An IEP or 504 Plan &amp; How To Help Your Child February 1 , 2018 Testing Window April 16 - May 25, 2018 Unit Timing- Grade 3 Unit Timing - Grades 4-5 Unit Timing - Grades 6-8 Unit Timing- Grades 9-11

844 views • 37 slides
TRILOBYTE SYSTEMS Consistent Timing Constraints with PrimeTime Steve Golson Trilobyte Systems

TRILOBYTE SYSTEMS Consistent Timing Constraints with PrimeTime Steve Golson Trilobyte Systems

TRILOBYTE SYSTEMS Consistent Timing Constraints with PrimeTime Steve Golson Trilobyte Systems http://www.trilobyte.com 2 Physical implementation Rule #1 Do not change the functionality Rule #2 Meet the specified timing constraints 3

512 views • 26 slides
SMT-based Probabilistic Analysis of Timing Constraints in Cyber-Physical Systems Li Huang 1 and

SMT-based Probabilistic Analysis of Timing Constraints in Cyber-Physical Systems Li Huang 1 and

SMT-based Probabilistic Analysis of Timing Constraints in Cyber-Physical Systems Li Huang 1 and Eun-Young Kang 12 , 1 School of Data &amp; Computer Science, Sun Yat-sen University, China huangl223@mail2.sysu.edu.cn 2 PReCISE Research Centre,

400 views • 8 slides
Analysis of Timing Constraints in Heterogeneous Middleware Interactions Ajay Kattepur 1 , Nikolaos

Analysis of Timing Constraints in Heterogeneous Middleware Interactions Ajay Kattepur 1 , Nikolaos

Analysis of Timing Constraints in Heterogeneous Middleware Interactions Ajay Kattepur 1 , Nikolaos Georgantas 2 , Georgios Bouloukakis 2 &amp; Valrie Issarny 2 1 PERC, TCS Innovation Labs, Mumbai, India 2 MiMove Team, Inria Paris-Rocquencourt,

575 views • 38 slides
20. Logic constraints, integer variables If-then constraints Generalized assignment

20. Logic constraints, integer variables If-then constraints Generalized assignment

CS/ECE/ISyE 524 Introduction to Optimization Spring 201718 20. Logic constraints, integer variables If-then constraints Generalized assignment problems Logic constraints Modeling a restricted set of values Sudoku! Laurent

475 views • 24 slides
Forecast constraints on cosmic strings from future CMB, pulsar timing and gravitational wave

Forecast constraints on cosmic strings from future CMB, pulsar timing and gravitational wave

Forecast constraints on cosmic strings from future CMB, pulsar timing and gravitational wave direct detection experiments Sachiko Kuroyanagi Univ. of Tokyo RESCEU (RESearch Center for the Early Universe) 12 Nov 2012 Based on S. Kuroyanagi,

657 views • 38 slides
Timing and Bandwidth Issues in Active Measurement or Physical Constraints on Active Probing

Timing and Bandwidth Issues in Active Measurement or Physical Constraints on Active Probing

Timing and Bandwidth Issues in Active Measurement or Physical Constraints on Active Probing MICRO-TUTORIAL ISMA 2003 Bandwidth Estimation Workshop (BEst) Darryl Veitch Essentials of Active Measurement Tap Tap

240 views • 7 slides
8/28/2010 CONTROL UNIT CPU is partitioned into Arithmetic Logic Unit (ALU) and Control Unit

8/28/2010 CONTROL UNIT CPU is partitioned into Arithmetic Logic Unit (ALU) and Control Unit

8/28/2010 CONTROL UNIT CPU is partitioned into Arithmetic Logic Unit (ALU) and Control Unit (CU) . The function of control unit is to generate relevant timing and control signals to all operations in the MANINDER KAUR computer.

295 views • 4 slides
Hardware Modeling 3 Timing Anomalies Peter Puschner slides credits: P. Puschner, R. Kirner, B.

Hardware Modeling 3 Timing Anomalies Peter Puschner slides credits: P. Puschner, R. Kirner, B.

Hardware Modeling 3 Timing Anomalies Peter Puschner slides credits: P. Puschner, R. Kirner, B. Huber VU 2.0 182.101 SS 2015 Timing Anomalies Obstacles to building

469 views • 33 slides
A Formal Framework for UML Modeling with Timed Constraints: Application to Railway Control

A Formal Framework for UML Modeling with Timed Constraints: Application to Railway Control

FRENCH NATIONAL INSTITUTE FOR TRANSPORT SAFETY AND RESEARCH A Formal Framework for UML Modeling with Timed Constraints: Application to Railway Control Systems Rafael Marcano Samuel Colin Georges Mariano Specification and Validation of UML

254 views • 24 slides
Outline 1 The topic 2 Decision support systems 3 Modeling 3.4 Constraints Computing with

Outline 1 The topic 2 Decision support systems 3 Modeling 3.4 Constraints Computing with

Outline 1 The topic 2 Decision support systems 3 Modeling 3.4 Constraints Computing with relations Finite domains Solution algorithms Complexity vs. completeness Model-Based Systems &amp; Qualitative Reasoning WS 11/12 EMDS 3

623 views • 21 slides
CONSENSUS Fall 2012 Ken Birman Consensus a classic problem Consensus abstraction underlies

CONSENSUS Fall 2012 Ken Birman Consensus a classic problem Consensus abstraction underlies

IMPOSSIBILITY OF CONSENSUS Fall 2012 Ken Birman Consensus a classic problem Consensus abstraction underlies many distributed systems and protocols N processes They start execution with inputs {0,1} Asynchronous,

511 views • 35 slides
Synchronous Batching: From Cascades to Free Routes Roger Dingledine The Free Haven Project

Synchronous Batching: From Cascades to Free Routes Roger Dingledine The Free Haven Project

Synchronous Batching: From Cascades to Free Routes Roger Dingledine The Free Haven Project Vitaly Shmatikov Paul Syverson SRI International Naval Research Laboratory Presented at PET 2004, May 27, 2004 Reminder: What does a mix do?

677 views • 28 slides
Lecture 4: Checking properties in NuSMV B. Srivathsan Chennai Mathematical Institute Model

Lecture 4: Checking properties in NuSMV B. Srivathsan Chennai Mathematical Institute Model

Lecture 4: Checking properties in NuSMV B. Srivathsan Chennai Mathematical Institute Model Checking and Systems Verification January - April 2016 1 / 43 Outline Module 1: Synchronous Vs Asynchronous composition Module 2: More examples

1.11k views • 90 slides
Consensus with Partial Synchrony Pedro Ferreira do Souto Departamento de Engenharia Informtica

Consensus with Partial Synchrony Pedro Ferreira do Souto Departamento de Engenharia Informtica

Consensus with Partial Synchrony Pedro Ferreira do Souto Departamento de Engenharia Informtica Faculdade de Engenharia Universidade do Porto Pedro F. Souto (FEUP) Consensus with Partial Synchrony 1 / 55 Outline Failure Detection 1

588 views • 57 slides
Shaahin Hessabi Department of Computer Engineering Sharif University of Technology D Design for

Shaahin Hessabi Department of Computer Engineering Sharif University of Technology D Design for

Shaahin Hessabi Department of Computer Engineering Sharif University of Technology D Design for Reuse i f R Design for reuse is an absolute necessity to: maintain productivity levels, keep the design time within reasonable

589 views • 21 slides
A multiplexer implementation Sum of products form: i 1 .c + i 0 .c Can be implemented

A multiplexer implementation Sum of products form: i 1 .c + i 0 .c Can be implemented

Lecture 7: Logic design Binary digital logic circuits: Two voltage levels (ground and supply voltage) for 0 and 1 Built from transistors used as on/off switches Analog circuits not very suitable for generic computing Digital

318 views • 17 slides
Introduction to Electrical Systems Course Code: EE 111 Course Code: EE 111 Department: Electrical

Introduction to Electrical Systems Course Code: EE 111 Course Code: EE 111 Department: Electrical

Introduction to Electrical Systems Course Code: EE 111 Course Code: EE 111 Department: Electrical Engineering Department: Electrical Engineering Instructor Name: B G Fernandes Instructor Name: B.G. Fernandes E mail id: bgf@ee iitb ac in E

217 views • 19 slides
A Conservative Extension of Synchronous Data-flow with State Machines a Jean-Louis Cola co,

A Conservative Extension of Synchronous Data-flow with State Machines a Jean-Louis Cola co,

A Conservative Extension of Synchronous Data-flow with State Machines a Jean-Louis Cola co, Bruno Pagano Marc Pouzet Esterel-Technologies (France) Universit e Paris-Sud (France) IFIP WG 2.11, Dagstuhl Jan. 26th, 2006 a presented at

772 views • 27 slides

More recommend