[PPT] - Unit-12: Modeling timing constraints B. Srivathsan Chennai PowerPoint Presentation

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Unit-12: Modeling timing constraints

B. Srivathsan

Chennai Mathematical Institute

NPTEL-course July - November 2015

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ATM Traffic lights controller Automatic gear control Flight control Pacemaker Controllers need to adhere to strict timing constraints

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ATM Traffic lights controller Automatic gear control Flight control Pacemaker

eg. when request for gear change is made, response should be within 1s

Controllers need to adhere to strict timing constraints

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How do we model-check systems with timing constraints?

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Adding time to transition systems

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Example 1

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TRAIN GATE

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TRAIN GATE far near in 1 2 3 up down approach enter exit approach lower exit raise lower raise

Train Controller Gate

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far near in 1 2 3 up down approach enter exit approach lower exit raise lower raise

Train Controller Gate

far, 0, up near, 1, up near, 2, down in, 1, up in, 2, down far, 3, down approach lower enter enter exit lower raise Train || Controller || Gate

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far near in 1 2 3 up down approach enter exit approach lower exit raise lower raise

Train Controller Gate

far, 0, up near, 1, up near, 2, down in, 1, up in, 2, down far, 3, down approach lower enter enter exit lower raise Train || Controller || Gate

Unsafe state: Train is in when gate is still up

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far near in 1 2 3 up down approach enter exit approach lower exit raise lower raise

Train Controller Gate

far, 0, up near, 1, up near, 2, down in, 1, up in, 2, down far, 3, down approach lower enter enter exit lower raise Train || Controller || Gate

Unsafe state: Train is in when gate is still up - need to add timing information in the model

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TRAIN GATE far near in 1 2 3 up down approach enter exit approach lower exit raise lower raise

Train Controller Gate after > 2 minutes after = 1 minute <= 1 minute execution time

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Coming next: Timed transition systems

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far near in 1 2 3 up down approach enter exit approach lower exit raise lower raise

Train Controller Gate

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far near in 1 2 3 up down approach enter exit approach lower exit raise lower raise

x := 0 x ≥ 2 Train Controller Gate

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far in near x ≤ 5 in x ≤ 5 1 2 3 up down approach enter exit approach lower exit raise lower raise

x := 0 x ≥ 2 Train Controller Gate

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far in near x ≤ 5 in x ≤ 5 1 2 3 up down approach enter exit approach lower exit raise lower raise

x := 0 x ≥ 2 y := 0 y == 1 Train Controller Gate

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far in near x ≤ 5 in x ≤ 5 1 2 3 up down approach enter exit approach lower exit raise lower raise

x := 0 x ≥ 2 y := 0 y == 1 y := 0 y == 1 Train Controller Gate

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far in near x ≤ 5 in x ≤ 5 1 2 3 up

comingdown

down

comingup

approach enter exit approach lower exit raise lower raise

x := 0 x ≥ 2 y := 0 y == 1 y := 0 y == 1 Train Controller Gate

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far in near x ≤ 5 in x ≤ 5 1 2 3 up

comingdown z ≤ 1

down

comingup z ≤ 1

approach enter exit approach lower exit raise lower raise

x := 0 x ≥ 2 y := 0 y == 1 y := 0 y == 1 z := 0 z := 0 Train Controller Gate

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far in near x ≤ 5 in x ≤ 5 1 2 3 up

comingdown z ≤ 1

down

comingup z ≤ 1

approach enter exit approach lower exit raise lower raise

x := 0 x ≥ 2 y := 0 y == 1 y := 0 y == 1 z := 0 z := 0 Train Controller Gate Reset Invariant Guard

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far in near x ≤ 5 in x ≤ 5 1 2 3 up

comingdown z ≤ 1

down

comingup z ≤ 1

approach enter exit approach lower exit raise lower raise

x := 0 x ≥ 2 y := 0 y == 1 y := 0 y == 1 z := 0 z := 0 Train Controller Gate Reset Invariant Guard Train || Gate || Controller

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far in near x ≤ 5 in x ≤ 5 1 2 3 up

comingdown z ≤ 1

down

comingup z ≤ 1

approach enter exit approach lower exit raise lower raise

x := 0 x ≥ 2 y := 0 y == 1 y := 0 y == 1 z := 0 z := 0 Train Controller Gate Reset Invariant Guard Train || Gate || Controller Synchronous product gives timed transition system for the joint behaviour

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Timed transition system

Transition system + Clocks

◮ Resets: to start measuring time ◮ Guards: to impose time constraint on action ◮ Invariants: to limit time spent in a state

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UPPAAL - Model-checker for timed transition systems

Kim Larsen, Paul Pettersson, Wang Yi - Computer-Aided Verification Award in 2013 for UPPAAL

www.uppaal.com

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UPPAAL demo

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UPPAAL demo

◮ Adding states, transitions and clocks ◮ Simulation environment ◮ (Subset of) CTL property verification

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Example 2

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x y p1 p2 p3

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x y p1 p2 p3 [1, 3] [1, 3] [1, 2]

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