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Tutorial Slides for Week 10
ENEL 353: Digital Circuits — Fall 2015 Term Steve Norman, PhD, PEng
Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Tutorial Slides for Week 10 ENEL 353: Digital Circuits Fall 2015 - - PowerPoint PPT Presentation
Tutorial Slides for Week 10 ENEL 353: Digital Circuits Fall 2015 - - PowerPoint PPT Presentation
Tutorial Slides for Week 10 ENEL 353: Digital Circuits Fall 2015 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 10 November, 2015 slide 2/11 ENEL 353 F15 Tutorial
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ENEL 353 F15 Tutorial Slides for Week 10
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Exercise 1: Moore FSMs and the clock divider
This is the general structure of a Moore FSM . . .
- utput
logic next state logic state next state k k M N inputs
- utputs
CLK
And this is a clock divider circuit . . .
CLK
Y
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ENEL 353 F15 Tutorial Slides for Week 10
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The clock divider circuit is just about the simplest possible Moore FSM. For the clock divider,
◮ What is M, the number of input bits? ◮ What is k, the number of state bits? ◮ What is N, the number of output bits? ◮ What is correct Boolean algebra for the next-state logic? ◮ What is correct Boolean algebra for the output logic?
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ENEL 353 F15 Tutorial Slides for Week 10
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Notes about notation for FSMs
Your ENEL 353 instructors will follow notation used in the course textbook. S0, S1, S2 and so on are names of states. Note that the numbers are the same size as the S, on the same level. S0, S1, S2 and so on are state bits—Q outputs of DFFs. Note that the numbers are subscripts. S′
i is the next value of the state bit Si.
Many books use the ′ operator for NOT. (For example, in those books A′ means what our textbook would write as A.) Watch out for that! In discussion of FSMs, some books use Qi for the ith state bit, and Q⋆
i for the next value of Qi.
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ENEL 353 F15 Tutorial Slides for Week 10
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Exercise 2
S′ S′
1
S′
2
S2 S0 S1 Y A r
CLK
R
For this Moore FSM, what are
◮ M, the number of inputs? ◮ k, the number of state
bits?
◮ the number of possible
states of the machine?
◮ N, the number of output
bits?
◮ next-state equations? ◮ output equations?
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ENEL 353 F15 Tutorial Slides for Week 10
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Exercise 2, continued
S′ S′
1
S′
2
S2 S0 S1 Y A r
CLK
R
Let’s add waveforms for S0, S1 and S2 to the timing diagram. Let’s assume synchronous reset for the three DFFs in the register.
1 1 1 CLK
R A
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ENEL 353 F15 Tutorial Slides for Week 10
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Remark about Exercise 2
We found the waveforms for S0, S1 and S2 based on rules about the behaviour of DFFs. Next week in lectures, we’ll see another method for solving the
- problem. The textbook calls this method, “Deriving an FSM
from its schematic.” Your instructors might sometimes call it “FSM analysis.”
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ENEL 353 F15 Tutorial Slides for Week 10
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Exercise 3: More DFF practice
r Q0 r r Q1 Q2 A R
CLK
Let’s add waveforms for Q0, Q1 and Q2 to the timing diagram.
1 1 1 CLK
R A
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ENEL 353 F15 Tutorial Slides for Week 10
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Exercise 4: Simple FSM design
Design an FSM with a single output bit, such that
◮ on reset the output goes to 0; ◮ when reset is turned off, the output repeats the sequence
- f 0 for one clock cycle, 1 for three cycles, 0 for one
cycle, 1 for three cycles, and so on.
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