Towards a DAQT TDR
May 2018
Towards a DAQT TDR May 2018 Contents of Phase 1 TDR Introduction : - - PowerPoint PPT Presentation
Towards a DAQT TDR May 2018 Contents of Phase 1 TDR Introduction : physics objectives, detector configuration Cross sections, luminosities, detector performance (tracking, EMC, PID ) Requirements ( event rates, event size, pile-up
May 2018
filtering capabilities, partitioning of DAQ, running modes…)
transport, FPGA based Compute Nodes, CPU/GPU farm, …)
(DQM)
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The PANDA readout consist of:
autonomous hit detection and data pre- processing (e.g. based on Sampling Analogue to Digital Converter)
(SODANET): single clock-source for PANDA (event correlation)
processing in FPGA (Field-Programmable Gate Array) 100101101
“large” vs. “small” cross sections
(needs to be checked by simulations)
cross section physics: 100
requires reduced luminosity due to storage limitations
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FrontEnd Electronics Data Concentrators Event(Burst)- Building Network FPGA based event filtering CPU/GPU based event filtering Storage 20 GB/s 20 GB/s 20 GB/s < 2GB/s <0.2 GB/s
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Next steps
Burst-building network:
burst-building network:
data processing (e.g. pre-clustering, at least time-ordered merging
Event building:
nodes (where final particle reconstruction will take place)
PC farm, final event filtering
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Work in Progress SODANET finished To be done Two options: 10 Gb Ethernet or Aurora links to PCIe card
Data format for transport between FEE/Data Concentrators and CN layer
independent of detector and DAQ layer
pixels etc.)
be STT wire number, MVD pixel ID etc.
Universal Packet Format (UPF)
SODANET to FEE and/or set by slow control in FEE for local runs):
control)
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Packet Header Packet Trailer Payload Header Payload Item 1 Payload Item N Payload Trailer
for a more compact data format
payload
crystal” or EMC cluster)
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(in particular, for MVD) ?
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