Today Power management Hardware capabilities Software management - - PowerPoint PPT Presentation
Today Power management Hardware capabilities Software management strategies Power and Energy Review Energy is power integrated over time 1 Watt == 1 Joule / second Heat depends on power consumption Battery life depends
Power management
Hardware capabilities Software management strategies
Energy is power integrated over time
1 Watt == 1 Joule / second
Heat depends on power consumption Battery life depends on energy consumption Both power and energy consumption must be
Processors are getting faster but using more power
Performance / Watt remains low
Battery capacities increase slowly Solutions:
Use a better VLSI process Have the system do less work Spread work across several smaller, slower processors Push the problem to the user
previous generation
Use power management techniques
Usable energy density increasing by ~10% / year Dominant rechargeable battery technology where
110-160 Wh/KG About 1/3 the energy density of dynamite!
In contrast…
Gasoline: 14,000 Wh/Kg Hydrogen: 38,000 Wh/Kg
Affected by:
Voltage
Toggling
Leakage
Voltage
Reduce power supply voltage
Toggling
Reduce activity Use simpler hardware These necessitate clock speed reductions
Leakage
Disconnect inactive parts from power supply
Applicable to processors, memories, etc
Not analog components
Disconnect parts from clock when not in use
Stops signal propagation
Pros:
Simple Fast – Stopping only clock distribution, not clock
generation
Cons:
Clock still runs, using power Does not prevent leakage
Disconnect parts from power supply when not in use Pros:
General Saves the most power
Con:
Long transition time
StrongARM variant for PDA-type devices
Small I- and D-caches Runs up to 200 MHz
Three power modes
Run – normal operation Idle – stops processor clock, I/O logic still powered Sleep – most chip activity shut down
Run → Sleep
30 µs – Flush CPU state to RAM 30 µs – Reset processor state 30 µs – Shut down clock
Sleep → Run
10 ms – Ramp up power supply 150 ms – Stabilize clock Small – Boot CPU
Power consumption during transition = Prun
Sleep
90 us 160 ms 10 us 10 us 90 us
Most peripherals can be independently powered
CPU modes: run, wait, doze, stop
STOP instruction puts a running processor into one of the
three power-saving modes
Interrupt can bring the CPU out of wait, doze, and stop No recovery time to bring CPU, SRAM, and flash out of any
power saving mode
Run mode – 75-290 mA @ 25 MHz Wait mode – 16 mA
CPU and memory clocks are stopped Peripherals continue to operate normally
Doze mode – 16 mA
Some peripherals are stopped, others keep running
Stop mode – 0.2-10 mA
All clocks stopped – peripherals do not operate Only external interrupts can wake the processor
Power is proportional to V2
Reduce power supply voltage → Save energy
Lower voltage necessitates reduced clock frequency
So we can trade off performance and lifetime on a set of
batteries
Why dynamic?
Observation: Often, peak CPU requirement >> average CPU
requirement
So: Run fast when we have to, run slow otherwise
Changing voltage takes time
To stabilize power supply and clock
Both continuous and discrete DVS exist
SA-1100 takes two voltages
3.3 V and 1.5 V
AMD K6-2
8 frequencies 200-600 MHz 1.4 V and 2.0 V 0.4 ms for voltage change
In the general case we have:
Some set of voltage choices Some set of frequency choices
works
Some set of power saving modes Some set of transition costs
These are all low-level mechanisms – A high-level
Static power management – Does not depend on
E.g., user-initiated suspend, hibernate, etc.
Dynamic power management – Automatically take
E.g. shut down functional units, change CPU frequency
Goal
Appropriately trade off between performance and power
consumption
Basic premises
Systems have non-uniform workloads It is possible to predict fluctuation in workload with some
degree of accuracy
probably remain busy for the next 1ms”
Need to figure out what the goal is For example:
Minimize power under performance constraints
Maximize performance under power constraints
Immediately sleep or idle the processor when there’s
Works well when transition times are short compared to idle
periods
Works poorly when transition times are relatively long
Need to do better than this…
Minimum idle time needed to make up for the cost of
Only beneficial to sleep the CPU if the idle time is longer
than this
Assume for now that…
No performance penalty is tolerated We know in advance the duration of idle periods
PTR: Power consumption during transition POn: Power consumption when active Assume PTR ≤ POn TBE of an inactive state is the total time for entering
TBE = TTR = TOn,Off + TOff,On Example:
TBE = 160 ms + 90 μs for SLEEP in SA-1100
Given an idle period Tidle > TBE Saved energy = (Tidle - TTR)(POn - POFF) + TTR(POn – PTR) Total energy that can be saved depends on
On real-world traces
In real life we don’t know the duration of idle times in
Solutions:
Use a fixed timeout – go to sleep after some amount of time Predict idle times based on past history
Also very important:
Disk, display, network interface, memory all use power Need to manage these as well
working sets
Reducing energy usage while providing advanced
Lots of implementation choices Leads to difficult system design problems
Clever power management schemes are often
Computing needs are increasing rapidly Battery capacities are increasing slowly Clever power management schemes can help
But too much cleverness is bad
Long-term solutions
Get help from the user HW accelerators for demanding application kernels Better power supplies