TIME DIVISION SWITCHING ETI 2506 – TELECOMMUNICATION SYSTEMS Saturday, 03 December 2016
PRINCIPLE OF TIME DIVISION SWITCHING • In TDM systems, speech is transmitted as PCM binary words. 1 • Sampled at 8,000 bits/sec, as sample occurs at 8.000 = 125 μ sec • Using contemporary digital technology, a sample can be passed from input to output of a switch in a small fraction of the 125 μ sec interval. • By dynamically assigning a number of input and output pairs, a digital switch can be used to transmit a number of speech samples simultaneously.
ANALOG TIME DIVISION SWITCH (PAM) SWITCH Bus Number of Simultaneous Conversations , SC 1 1 SC = 125 𝑢 𝑡 2 2 Where 𝑢 𝑡 is the time required by the cyclic controller to set up the connection and transfer the data sample. N N Operation Mode Non-blocking but not fully available, i.e not possible to k to 2 k Modulo-N connect any input to any 𝒎𝒑𝒉 𝟑 N = k decorder Counter output. Clock Cyclic control
INPUT-CONTROLLED TIME DIVISION SWITCH Bus 1 1 2 2 N N k to 2 k Modulo-N Contents of MAR Address Counter/MAR decoder 1-5 Clock decoder/MDR 2-3 Cyclic control 3-7 . . MAR – Memory Address Register MDR – Memory Data Register . N-N
OUTPUT-CONTROLLED TIME DIVISION SWITCH Bus 1 1 2 2 N N Contents of MAR Clock 1-5 Address Decoder/ k to 2 k Modulo-N MDR decoder Counter/MAR 2-3 3-7 Cyclic control . . MAR – Memory Address Register . MDR – Memory Data Register N-N
CAPACITY OF TIME DIVISION SWITCH Switch capacity, SC is given by: 125 SC = 𝑢 𝑗 +𝑢 𝑛 +𝑢 𝑒 +𝑢 𝑢 Where t i = time to increment modulo N counter in μ sec t m = time to read from the control memory t d = time to decode address and to select inlet or outlet t t = time to transfer sample from inlet to outlet
GENERALIZED TIME DIVISION SWITCH 1 1 2 2 N N Decoder Decoder Clock Input data Modulo-N Memory Data Register (MDR) Counter Control Memory Memory Address Register (MAR)
Serial to Parallel to Data Memory Parallel Serial N words of 8 bits each Converter Converter Modulo N Memory Address Counter Register Memory Data Register Memory Address Control Memory Register N words of k bits each
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