TIME DIVISION SWITCHING ETI 2506 TELECOMMUNICATION SYSTEMS - - PowerPoint PPT Presentation

TIME DIVISION SWITCHING

ETI 2506 – TELECOMMUNICATION SYSTEMS Saturday, 03 December 2016

PRINCIPLE OF TIME DIVISION SWITCHING

• In TDM systems, speech is transmitted as PCM binary

words.

• Sampled at 8,000 bits/sec, as sample occurs at

1 8.000 =

125μsec

• Using contemporary digital technology, a sample can be

passed from input to output of a switch in a small fraction

• f the 125 μsec interval.
• By dynamically assigning a number of input and output

pairs, a digital switch can be used to transmit a number of speech samples simultaneously.

k to 2k decorder Modulo-N Counter Cyclic control Bus 1 2 N 1 2 N

ANALOG TIME DIVISION SWITCH (PAM) SWITCH

Number of Simultaneous Conversations , SC SC = 125

𝑢𝑡

Where 𝑢𝑡 is the time required by the cyclic controller to set up the connection and transfer the data sample. Clock 𝒎𝒑𝒉𝟑N = k Operation Mode Non-blocking but not fully available, i.e not possible to connect any input to any

• utput.

Bus 1 2 N 1 2 N k to 2k decoder Modulo-N Counter/MAR Cyclic control Clock Address decoder/MDR 1-5 2-3 3-7 . . . N-N

INPUT-CONTROLLED TIME DIVISION SWITCH

MAR – Memory Address Register MDR – Memory Data Register Contents of MAR

Bus 1 2 N 1 2 N Modulo-N Counter/MAR k to 2k decoder Cyclic control 1-5 2-3 3-7 . . . N-N MAR – Memory Address Register MDR – Memory Data Register Contents of MAR Clock Address Decoder/ MDR

OUTPUT-CONTROLLED TIME DIVISION SWITCH

Switch capacity, SC is given by: SC =

125 𝑢𝑗+𝑢𝑛+𝑢𝑒+𝑢𝑢

Where ti = time to increment modulo N counter in μsec tm = time to read from the control memory td = time to decode address and to select inlet or outlet tt = time to transfer sample from inlet to outlet

CAPACITY OF TIME DIVISION SWITCH

1 2 N 1 2 N Decoder Decoder Memory Data Register (MDR) Control Memory Memory Address Register (MAR) Modulo-N Counter Clock Input data

GENERALIZED TIME DIVISION SWITCH

Data Memory N words of 8 bits each Memory Address Register Memory Data Register Control Memory N words of k bits each Memory Address Register Modulo N Counter Serial to Parallel Converter Parallel to Serial Converter