thermal stability of sic jfets in conduction mode
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Thermal stability of SiC JFETs in conduction mode EPE 2013 Rmy O - PowerPoint PPT Presentation

Thermal stability of SiC JFETs in conduction mode EPE 2013 Rmy O UAIDA , Cyril B UTTAY , Raphal R IVA , Dominique B ERGOGNE , Christophe R AYNAUD , Florent M OREL , Bruno A LLARD Laboratoire Ampre, Lyon, France 4/9/13 Thermal stability of


  1. Thermal stability of SiC JFETs in conduction mode EPE 2013 Rémy O UAIDA , Cyril B UTTAY , Raphaël R IVA , Dominique B ERGOGNE , Christophe R AYNAUD , Florent M OREL , Bruno A LLARD Laboratoire Ampère, Lyon, France 4/9/13 Thermal stability of SiC JFETs 1/21

  2. Outline Introduction JFET Characterization Experimental study of the runaway condition Conclusions Thermal stability of SiC JFETs 2/21

  3. Plan Introduction JFET Characterization Experimental study of the runaway condition Conclusions Thermal stability of SiC JFETs 3/21

  4. Maximum operating temperature – Theory 3000°C Silicon 3C−SiC 6H−SiC 2500°C 4H−SiC 2H−GaN Junction temperature Diamond 2000°C 1500°C 1000°C 500°C 0°C 10 V 100 V 1 kV 10 kV 100 kV 1 MV Breakdown voltage ◮ Silicon operating temp is intrisically limited at high voltages. ◮ Wide-bandgap semiconducors (inc. SiC) go much higher Thermal stability of SiC JFETs 4/21

  5. Maximum operating temperature – Practically Example: SiCED JFET: material max. temp. cause Semiconductor SiC 2730° C sublimation backside metal Ag 962° C melting point Top metallization Al 660° C melting point second. passivation polyimide 500-620° C decomposition ◮ Most of these limitations can be overcome by the die manufacturer (e.g topside metal) ◮ Other will depend on the packaging technology ◮ Case material (ceramic, plastic. . . ) ◮ Solder alloys, etc. ➜ T J > 300° C is possible Thermal stability of SiC JFETs 5/21

  6. Maximum operating temperature – Practically Example: SiCED JFET: material max. temp. cause Semiconductor SiC 2730° C sublimation backside metal Ag 962° C melting point Top metallization Al 660° C melting point second. passivation polyimide 500-620° C decomposition ◮ Most of these limitations can be overcome by the die manufacturer (e.g topside metal) ◮ Other will depend on the packaging technology ◮ Case material (ceramic, plastic. . . ) ◮ Solder alloys, etc. ➜ T J > 300° C is possible Thermal stability of SiC JFETs 5/21

  7. Maximum operating temperature – Practically Example: SiCED JFET: material max. temp. cause Semiconductor SiC 2730° C sublimation backside metal Ag 962° C melting point Top metallization Al 660° C melting point second. passivation polyimide 500-620° C decomposition ◮ Most of these limitations can be overcome by the die manufacturer (e.g topside metal) ◮ Other will depend on the packaging technology ◮ Case material (ceramic, plastic. . . ) ◮ Solder alloys, etc. ➜ T J > 300° C is possible Thermal stability of SiC JFETs 5/21

  8. Maximum operating temperature – Practically Example: SiCED JFET: material max. temp. cause Semiconductor SiC 2730° C sublimation backside metal Ag 962° C melting point Top metallization Al 660° C melting point second. passivation polyimide 500-620° C decomposition ◮ Most of these limitations can be overcome by the die manufacturer (e.g topside metal) ◮ Other will depend on the packaging technology ◮ Case material (ceramic, plastic. . . ) ◮ Solder alloys, etc. ➜ T J > 300° C is possible Thermal stability of SiC JFETs 5/21

  9. Reduced cooling Take advantage of the high junction temp. capability of SiC devices to save on thermal management ◮ Operation in milder ambient ◮ Reduction in ◮ Volume, weight ◮ Complexity (passive vs active) ◮ Many applications: ◮ Transports ◮ Low-maintenance, high-rel. Source: APEI [1]. Converter operating at 150° C ambient, with 250° C junction temperature, using passive cooling. Thermal stability of SiC JFETs 6/21

  10. Reduced cooling Take advantage of the high junction temp. capability of SiC devices to save on thermal management ◮ Operation in milder ambient ◮ Reduction in ◮ Volume, weight ◮ Complexity (passive vs active) ◮ Many applications: ◮ Transports ◮ Low-maintenance, high-rel. Source: APEI [1]. Converter operating at 150° C ambient, with 250° C junction temperature, using passive cooling. ➜ Thermal runaway issues must be considered Thermal stability of SiC JFETs 6/21

  11. Thermal Run-away mechanism – Principle ◮ an imaginary device ◮ its associated cooling system ◮ in region A, the device dissipates more than the cooling system can extract ◮ in region B, the device dissipates less than the cooling system can extract ◮ two equilibrium points: one stable and one unstable ◮ above the unstable point, run-away occurs Thermal stability of SiC JFETs 7/21

  12. Thermal Run-away mechanism – Principle ◮ an imaginary device ◮ its associated cooling system ◮ in region A, the device dissipates more than the cooling system can extract ◮ in region B, the device dissipates less than the cooling system can extract ◮ two equilibrium points: one stable and one unstable ◮ above the unstable point, run-away occurs Thermal stability of SiC JFETs 7/21

  13. Thermal Run-away mechanism – Principle ◮ an imaginary device ◮ its associated cooling system ◮ in region A, the device dissipates more than the cooling system can extract ◮ in region B, the device dissipates less than the cooling system can extract ◮ two equilibrium points: one stable and one unstable ◮ above the unstable point, run-away occurs Thermal stability of SiC JFETs 7/21

  14. Thermal Run-away mechanism – Principle ◮ an imaginary device ◮ its associated cooling system ◮ in region A, the device dissipates more than the cooling system can extract ◮ in region B, the device dissipates less than the cooling system can extract ◮ two equilibrium points: one stable and one unstable ◮ above the unstable point, run-away occurs Thermal stability of SiC JFETs 7/21

  15. Thermal Run-away mechanism – Principle ◮ an imaginary device ◮ its associated cooling system ◮ in region A, the device dissipates more than the cooling system can extract ◮ in region B, the device dissipates less than the cooling system can extract ◮ two equilibrium points: one stable and one unstable ◮ above the unstable point, run-away occurs Thermal stability of SiC JFETs 7/21

  16. Thermal Run-away mechanism – examples Always stable Thermal stability of SiC JFETs 8/21

  17. Thermal Run-away mechanism – examples Always stable Always unstable Thermal stability of SiC JFETs 8/21

  18. Thermal Run-away mechanism – examples Always stable Always unstable Becomming unstable with ambient temperature rise Thermal stability of SiC JFETs 8/21

  19. Aim of the study ◮ JFETs can operate at high temperature ◮ We might take advantage of this to size the cooling system down Thermal stability of SiC JFETs 9/21

  20. Aim of the study ◮ JFETs can operate at high temperature ◮ We might take advantage of this to size the cooling system down Thermal stability of SiC JFETs 9/21

  21. Aim of the study ◮ JFETs can operate at high temperature ◮ We might take advantage of this to size the cooling system down Is there a risk of thermal runaway of JFETs? Thermal stability of SiC JFETs 9/21

  22. Plan Introduction JFET Characterization Experimental study of the runaway condition Conclusions Thermal stability of SiC JFETs 10/21

  23. Test configuration ◮ High temperature test system ◮ Silver-sintered interconnects ◮ Ceramic substrate (DBC) ◮ Copper-kapton leadframe ◮ DUT: 500 m Ω SiC JFET from SiCED ◮ characterization: ◮ Tektronix 371A curve tracer ◮ Thermonics T2500-E conditionner Thermal stability of SiC JFETs 11/21

  24. Test configuration ◮ High temperature test system ◮ Silver-sintered interconnects ◮ Ceramic substrate (DBC) ◮ Copper-kapton leadframe ◮ DUT: 500 m Ω SiC JFET from SiCED ◮ characterization: ◮ Tektronix 371A curve tracer ◮ Thermonics T2500-E conditionner Thermal stability of SiC JFETs 11/21

  25. Test configuration ◮ High temperature test system ◮ Silver-sintered interconnects ◮ Ceramic substrate (DBC) ◮ Copper-kapton leadframe ◮ DUT: 500 m Ω SiC JFET from SiCED ◮ characterization: Source: Thermonics T-2500SE Datasheet ◮ Tektronix 371A curve tracer ◮ Thermonics T2500-E conditionner Thermal stability of SiC JFETs 11/21

  26. Static Characterization over a wide temperature range 12 -50 ◦ C -10 ◦ C 10 30 ◦ C 70 ◦ C Forward current [A] 8 110 ◦ C 150 ◦ C 6 190 ◦ C 230 ◦ C 270 ◦ C 4 300 ◦ C 2 0 0 2 4 6 8 10 12 Forward voltage [V] V GS = 0 V , i.e. device fully-on Thermal stability of SiC JFETs 12/21

  27. Power dissipation as a function of the junction temp. 2.0 A 140 4.0 A 6.0 A 120 Dissipated power [W] 8.0 A 100 10.0 A 80 60 40 20 0 50 0 50 100 150 200 250 300 Temperature [C] Thermal stability of SiC JFETs 13/21

  28. Power dissipation as a function of the junction temp. 1K/W 2.0 A 140 2K/W 4.0 A 6.0 A 120 Dissipated power [W] 8.0 A 100 10.0 A 80 W / K 5 60 . 4 40 8K/W 20 0 50 0 50 100 150 200 250 300 Temperature [C] Thermal stability of SiC JFETs 13/21

  29. Power dissipation as a function of the junction temp. 1K/W 2.0 A 140 4.0 A 6.0 A 120 Dissipated power [W] 2K/W 8.0 A 100 10.0 A 80 60 W / K 40 5 . 4 8K/W 20 0 50 0 50 100 150 200 250 300 Temperature [C] Thermal stability of SiC JFETs 13/21

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