Test and Verification Solutions The Verification Experts Essentials for Developing and Deploying SV-based VIP DV Club Presentation (23 April 2012)
NEED FOR VERIFICATION IP
Why do we need VIPs? • Time To Market – Ready-to-integrate models accelerate development • Quality – Improve thoroughness of verification using VIP with pre-defined tests, coverage models, assertions, … – Demonstrate compliance to a protocol – Demonstrate compliance to a protocol – Licensing (or buying) VIP imports knowledge • Reduce costs – Increase re-use • Vertical: use VIP at block and SoC level • Horizontal: use VIP across multiple chips • Industry: External VIP should be cheaper to license (or buy) than make – Does VIP cost less to use than it for you to develop it?
Benefits Of Using SysV based OVM/UVM VIPs • Easier Integration and Reduced Number of Bugs During Integration into Multiple SOC Platforms – Sequences particular to a VIP Developed for one SOC project can be reused in other SOC projects without any change because there is no hierarchical access to sequences or configuration details of the VIP in OVM/UVM Methodology. Higher Flexibility for the User both at Chip and Block Level • – Block Level Sequences Are Easily Portable at Chip Level – VIP Configurations developed in the Block Level are accessible at the Chip Level • • Reduce the Development Time for Newer VIP’s Reduce the Development Time for Newer VIP’s – Having generic components built for specific protocols enable to reduce the TAT in the development of newer protocols of similar type – Example VIP Families that can share generic components • Slow Speed Serial Protocols (I2C/I2S/SPI/UART/GPIO etc..) • ARM Interconnects (APB/AHB/AXI) • MIPI Protocols • Storage Protocols (SDCARD/SDIO etc....) • Multi-Language Support and Methodology Migration – SysV based UVM/OVM works well with other verification languages like “e” and SystemC • Multiple Simulator Support – Cadence, Mentor, Synopsys, Aldec – Support (OVM/UVM & SystemVerilog)
Additional Benefits of System Verilog VIP’s • HDL days: – HDLs do not support object oriented programming, constraint based randomization, assertion feature and functional coverage – Need for PSL or OVL languages for writing assertions • With System Verilog: – User can dynamically create the object based on object oriented programming – Supports assertion – no need for PSL or OVL – Most simulators support the Systemverilog language – Use of “define” option switch for work around
STEPS FOR DEVELOPING VERIFICATION IP
Generic Component • Creating Generic Components (OVM/UVM) [Seq Item, Driver, Monitor etc..] for a particular type of Protocol [Eg. Serial Communications family like I2C, I2S, UART, GPIO, SPI] enables reusability and new VIP can inherit major functionality from the generic components. • This idea can be extended to protocols of similar types example – [USB3, PCIe3, SRIO etc..] or [DDR, Flash, SD Standards] or SOC Interconnect [ARM/PLB/OPB/VBUS] • Example Generic Components: – generic sequence item extend ovm_sequence_item, – generic sequencer extends ovm_sequencer, – generic sequence base enxteds ovm_sequencer, – generic driver extends ovm_driver, – generic monitor extends ovm_monitor, – generic bus monitor extends ovm_bus_monitor, – generic interface
Generic Component - Example Generic ======= class tvs_sio_generic_slave_sequence_item extends ovm_sequence_item; // generic variables bit gen_tx[]; bit gen_rx[]; endclass SPI Protocol Example =================== =================== class tvs_sio_spi_slave_sequence_item extends tvs_sio_generic_slave_sequence_item; virtual function void generateNewData(); gen_tx = new[spi_tx_size]; gen_rx = new[spi_tx_size]; for (int i = 0; i < spi_tx_size; i++) begin gen_tx[i] = $urandom; end endfunction: generateNewData endclass
Generic Component - Example I2C Example =========== Class tvs_sio_i2c_slave_item extends tvs_sio_generic_slave_sequence_item virtual function update_address(); int index; if(gen_rx.size() == 9)begin if(fb_desc == TVS_I2C_7BIT)begin for(int i=0;i<=6; i++) address[6-i] = gen_rx[i]; end end else if(fb_desc == TVS_I2C_10BIT && rnw == 0)begin address[9:8] = {gen_rx[5],gen_rx[6]}; end end else if(gen_rx.size() == 18 && fb_desc != TVS_I2C_7BIT)begin address[7:0] = {gen_rx[9],gen_rx[10],gen_rx[11],gen_rx[12],gen_rx[13],gen_rx[14], gen_rx[15],gen_rx[16]}; end endfunction
Developing Reusable Sequences OVM/UVM Methodology sequence can be used in VIP based verification, • across any project • we can reuse the same sequences without any changes and also the Virtual Sequencer For Both Chip and Block to be extended from OVM or UVM Sequencer. Before writing the sequence we should provide the following flexibility: • – – User controllability User controllability – Randomization – Randomly select sequence Based on do_sequence_kind option we can randomly select the • sequences from the sequence lib. – Write followed by read – Read followed by write – Write followed by write – Read followed by read – Error scenario
Sequence Reuse - illustration MIPI-RFFE Sequences =================== 1386 virtual task body(); 1388 for(int i =0; i<=10000; i++) 1389 begin 1390 assert( this.randomize(seq_kind) with {seq_kind inside { get_seq_kind("tvs_sio_rffe_reg_0_wr_cmd_sequence_err_inj") , 1391 get_seq_kind("tvs_sio_rffe_reg_wr_cmd_sequence_err_inj"), 1392 get_seq_kind("tvs_sio_rffe_reg_rd_cmd_sequence_err_inj"), 1392 get_seq_kind("tvs_sio_rffe_reg_rd_cmd_sequence_err_inj"), 1393 get_seq_kind("tvs_sio_rffe_reg_ext_wr_cmd_sequence_err_inj"), 1394 get_seq_kind("tvs_sio_rffe_reg_ext_rd_cmd_sequence_err_inj"), 1395 get_seq_kind("tvs_sio_rffe_reg_ext_wr_long_cmd_sequence_err_inj"), 1396 get_seq_kind("tvs_sio_rffe_reg_ext_rd_long_cmd_sequence_err_inj"), 1397 get_seq_kind("tvs_sio_rffe_rsvd_cmd_sequence_err_inj") 1398 }; 1399 }); 1400 1401 do_sequence_kind(seq_kind); 1402 end 1403 endtask
Agile approach to New VIP Development • New VIP Development and Delivery to customer • Using an Agile Software Development Methodology helps with – Meeting customer schedule for testing features – Reduces bug rates Phase 1 Delivery: • – Basic Transactions with end to end capability {Driver, Monitor, Scoreboard and Sequencer and Sequences} – May only do a basic write and read – Allows the developer and User to do a lot of pipe cleaning and also integrate major feedback on Integration issues and also incorporate major feedbacks on Code format and Structures • Subsequent Phase Delivery: – Subsequent release deliver VIP features based on customer phased plan – Decide if deliver is schedule driven (i.e. deliver as many new features as possible on this date) or feature driven (deliver these features as soon as possible) – Checker and functional coverage feature support (i.e. tests to achieve 100% coverage) are often delayed until the final deliveries
Phasing it out…. Agile delivery ��������������������������� ��������
Migrating OVC or UVC into E Testbenches • Companies who have legacy databases in e/ERM need not worry about migrating to OVM/UVM or having to integrate newer VIP’s which are built in SYSV based in OVM or UVM. The following needs to be done to integrate SV based VIP’s into E Testbenches UVMize eVC’s Automation Possible Generate e Wrapper for SV- Generate e Wrapper for SV- UVM VIP and Integrate into “E” Testbench Automation Possible using UIG Tool from Cadence Testbench Infrastructure Changes END Process SV Sequences can be initiated from “E” Virtual Sequencer
Migrating OVC or UVC into E Testbenches • Example For Migrating from eRM to UVMe eRM unit tvs_tdm_bfm_u { -- This field is a pointer to the sequence driver. driver: tvs_tdm_driver_u; --reference Signal map unit at Bfm Unit smp: tvs_tdm_smp_u; --sequence item sequence_item: tvs_tdm_item_s; } UVM-e unit tvs_tdm_bfm_u like uvm_bfm -- Change { -- This field is a pointer to the sequence driver. driver: tvs_tdm_driver_u; --reference Signal map unit at Bfm Unit smp: tvs_tdm_smp_u; --sequence item sequence_item: tvs_tdm_item_s; }
Migration of eVC to UVM and Integration of eVC Into SV Testbench START UVMize eVC’s Automation Possible Generate SV API using UIG Generate SV API using UIG Tools from Cadence for access to Configuration/Sequences and Monitor Testbench Infrastructure Changes END Process E Sequences can be initiated from SV Virtual Sequencer
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