Spring 2015 Week 9 Module 53 Digital Circuits and Systems Closing Remarks Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay
Acknowledgements Prof. Dinesh Bhatia and Prof. Poras Balsara of Univ. Of Texas at Dallas Teaching Assistants at IIT Madras Praveen Alapati Dennis Antony Varkey S R Swami Saranam Biswabandan Panda Gnaneswara Jonna 2
Acknowledgements IIT Bombay (NPTEL Team) Producer: Arun Kalwankar Project Manager: Sangeeta Shrivatsava Digital Video Editor: Tushar Deshpande Digital Video Cameraman: Amin Shaikh Vijay Kedare, Ravi Paswan, Vinay Raut IIT Madras (NPTEL Team) Project Officer: Bharathi Balaji Project Associate: T. Senthil Kumar Prof. Andrew Thangaraj 3
Acknowledgements Course Platform Abhinav Khandelwal, Ashwani Sharma and the rest of the team at Google Victor Lyuboslavsky of EDA Platform Exam co-ordination team of TCS 4
Quick Outline Introduction, basic Boolean logic, theorems, minimization K-Maps Combinational circuits Sequential Elements and Circuits CMOS, Delays, State machines FSMs, state machine synthesis, state minimization, assignment Datapath + controlpath Pipelining, parallelism, interleaving Arithmetic circuits Verilog Modeling 5
Handling Complexity
Read up Memory design Full system design High speed arithmetic circuits Power/Energy analysis Verification of verilog designs Large scale projects 7
About the Course 10,000+ Students More than 1000 active students Mix of students, faculty, industry participants Good response in assignments and quizzes More participation in the forums required 8
End of Week 9: Module 53 Thank You Closing Remarks 9
Recommend
More recommend
