Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras
*Currently a Visiting Professor at IIT Bombay
Digital Circuits and Systems
Spring 2015 Week 9 Module 53
Closing Remarks
Systems Closing Remarks Shankar Balachandran* Associate Professor, - - PowerPoint PPT Presentation
Spring 2015 Week 9 Module 53 Digital Circuits and Systems Closing Remarks Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay Acknowledgements
Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras
*Currently a Visiting Professor at IIT Bombay
Closing Remarks
Prof. Dinesh Bhatia and Prof. Poras Balsara of Univ. Of
Teaching Assistants at IIT Madras
Praveen Alapati Dennis Antony Varkey S R Swami Saranam Biswabandan Panda Gnaneswara Jonna
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IIT Bombay (NPTEL Team)
Producer: Arun Kalwankar Project Manager: Sangeeta Shrivatsava Digital Video Editor: Tushar Deshpande Digital Video Cameraman: Amin Shaikh Vijay Kedare, Ravi Paswan, Vinay Raut
IIT Madras (NPTEL Team)
Project Officer: Bharathi Balaji Project Associate: T. Senthil Kumar Prof. Andrew Thangaraj
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Course Platform
Abhinav Khandelwal, Ashwani Sharma and the rest of the team at
Victor Lyuboslavsky of EDA Platform Exam co-ordination team of TCS
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Introduction, basic Boolean logic, theorems, minimization K-Maps Combinational circuits Sequential Elements and Circuits CMOS, Delays, State machines FSMs, state machine synthesis, state minimization,
Datapath + controlpath Pipelining, parallelism, interleaving Arithmetic circuits Verilog Modeling
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Memory design Full system design High speed arithmetic circuits Power/Energy analysis Verification of verilog designs Large scale projects
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10,000+ Students More than 1000 active students Mix of students, faculty, industry participants Good response in assignments and quizzes More participation in the forums required
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Closing Remarks 9