Systems Flipflops Shankar Balachandran* Associate Professor, CSE - - PowerPoint PPT Presentation

Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 4 Module 20

Flipflops

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D Flip-flop

 The D latch has a shortcoming – the inputs should not

change while the gate signal is asserted (otherwise there are multiple asynchronous state changes which can lead to problems in a circuit).

 One solution is to design the circuit so that state changes

• ccur during clock edges rather than during clock levels –

this type of device is called edge-triggered (i.e., flip-flop).

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Edge-Triggering: Master-Slave D FF

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Master-Slave Timing Diagram

 Example: When CLK is high, output of master is allowed to change

with D; when CLK is low (falling edge), the output of the master is fixed and propagated through to the output of the slave  this flip- flop triggers on falling or negative edge. CLK D Q* Q* 1 1 1

Characteristic Table

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Summary: Level vs Edge Triggering

CLK D QA QB QC QA QB QC D Q Q

CLK

D Q Q

Λ

D Q Q

Λ

CLK D

A: Latch B: +ve Edge trigerred DFF C: -ve Edge trigerred DFF

Flip Flop with Preset and Clear

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PRESET_n CLEAR_n

PRESET_n CLEAR_n

D-Flip Flop With Synchronous Clear

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T-Flip Flop

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 A T flip-flop changes state on every clock if it is enabled

(T=“1”). It can be implemented by connecting together the J and K inputs of a JK flip-flop.

End of Week 4: Module 20

Thank You

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