Systems Gated Latches Shankar Balachandran* Associate Professor, - - PowerPoint PPT Presentation

Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 4 Module 19

Gated Latches

Gated SR Latch

Gated Latches 2

Clk S R Q(t+1) 1 Q(t) 1 1 1 1 1 1 1 1

Undefined

X X Q

S R Clk Q Q

Gated SR Latch with NAND Gates

CLK S R Q(t+1) 1 Q(t) 1 1 1 1 1 1 1 1

Undefined

X X Q

 Still have problems with 11 inputs to SR latch  One solution is to define the condition away: never allow both inputs

to the SR to have the same value.

Gated Latches

Gated Latches 4

Gated D latch

 D (data) latch does not allow both inputs to an SR latch to have the

same value.

 A register is an array of D latches or flip-flops which share a

common gate/clock – this is a fundamental building block for computer design. G D Q(t+1) Q(t+1) 1 0 1 1 1 1 0 X Q(t) Q(t)

Characteristic Table

Gated Latches 5

Synchronous versus Asynchronous

 Sequential circuits can be.

 Asynchronous or.  Synchronous.

 Asynchronous Sequential Circuits: State changes can

• ccur at any time.

 Synchronous Sequential Circuits: State changes can

• ccur only in conjunction with a reference timing signal.

This signal is generally known as the clock signal of the system.

 For the most part, we will consider only synchronous

circuits in this class.

Gated Latches 6

Clocking of Synchronous Circuits:

 Clock signals are usually periodic.  Duty cycle = ON Time / Clock Period  Frequency = 1/Time Period

 Units are in Hz

Issues with Latches

 Latches are level sensitive:

 For example:

 In a D-Latch, if G is ON, multiple changes to D will be propagated to

the output

 This can in turn result in undesirable results

Gated Latches 7

End of Week 4: Module 19

Thank You

Gated Latches 8