Systems More Sequential Circuits Shankar Balachandran* Associate - - PowerPoint PPT Presentation
Spring 2015 Week 5 Module 26 Digital Circuits and Systems More Sequential Circuits Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay Frequency
Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras
*Currently a Visiting Professor at IIT Bombay
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CLK Q0 Q1 f f/2 f/4 T Q Q
“1” Q0 CLK T Q Q
“1” Q1
T Q Q Clock T Q Q T Q Q 1 Q Q
1
Q
2
(a) Circuit
Clock Q Q
1
Q
2
Count 1 2 3 4 5 6 7
(b) Timing diagram
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T Q Q Clock T Q Q T Q Q 1 Q Q
1
Q
2
(a) Circuit
Clock Q Q
1
Q
2
Count 7 6 5 4 3 2 1
(b) Timing diagram
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5
Counters are asynchronous
The flipflops are not all synchronized to the same clock
A big enough width of the counter can upset the counting
Flip flop 0’s output delays flip flop1 Flip flop 1’s output delays flip flop 2 . . .
Need for a counter that works “synchronously” w.r.to
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1 1 1 1 1 2 3 1 1 4 5 6 1 1 7 1 1 1 1 Clock cycle 0 0 8 Q
2
Q
1
Q Q
1
changes Q
2
changes Q0 toggles every clock cycle Q1 toggles every time Q0 changes from 1 to 0 Q2 toggles every time Q1 is at 1 and Q0 changes from 1 to 0 Question: When should Q3 toggle?
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T Q Q Clock T Q Q T Q Q 1 Q Q
1
Q
2
(a) Circuit
Clock Q Q
1
Q
2
Count 0 1 2 3 5 9 12 14
(b) Timing diagram
T Q Q Q
3
Q
3
4 6 8 7 10 11 13 15 1
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T Q Q Clock T Q Q Enable Clear_n T Q Q T Q Q
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Enable Q Q
1
Q
2
D D
1
D
2
Load Clock 1 Clock 1 2 3 4 5 1 Clock Count Q Q
1
Q
2
(a) Circuit (b) Timing diagram
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Reading Exercises
T Q Q Clock T Q Q T Q Q 1 Q Q
1
Q
2
(a) Circuit
Clock Q Q
1
Q
2
Count
(b) Timing diagram
1 2 3 4 5 1 2
Asynchronous Mod-6 Counter
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