Systems State Machines 2: Design Problems Shankar Balachandran* - - PowerPoint PPT Presentation

Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 6 Module 30

State Machines 2: Design Problems

Analysis and Design of Sequential Logic Circuits 2

Example 1:



Design a sequential circuit that produces “1” on its output if it detects the sequence “101” on it’s input. The detector should keep checking for the appropriate sequence and should not reset to the initial state after it has recognized the sequence.

P.S. Q1Q0 N.S. (Q1*Q0*) Out (z) x=0 x=1 x=0 x=1 s0 (00) s0 (00) s1 (01) s1 (01) s2 (10) s1 (01) s2 (10) s0 (00) s1 (01) 1

1 1

Q x z x D Q x D   

Moore Style

Analysis and Design of Sequential Logic Circuits 3

1 1 1

Q Q z x D Q Q x Q x D     P.S. Q1Q0 N.S. (Q1*Q0*) Out (z) x=0 x=1 s0 (00) s0 (00) s1 (01) s1 (01) s2 (10) s1 (01) s2 (10) s0 (00) s3 (11) s3 (11) s2 (10) s1 (01) 1

Analysis and Design of Sequential Logic Circuits 4

Example (contd.): Output Waveforms

Mealy outputs may change when an input changes (i.e., not necessarily on a clock edge). output may have glitches. This problem can be solved by making Mealy inputs synchronous. Moore outputs only change on clock edges since they depend only on the present state. Moore outputs may be delayed w.r.t. the corresponding outputs in a Mealy implementation. CLK Input x State Output z Mealy State Output z Moore s0 s1 s2 s1 s1 s2 s1 s1 s2 s0 s0 s1 s2 s3 s1 s2 s3 s1 s2 s0

Analysis and Design of Sequential Logic Circuits 5

Example 2:

A sequential circuit has one input and one output. When input sequence “110” occurs the output becomes 1 and remains 1 until the sequence “110” occurs again in which case the output returns to 0. The output remains 0 until “110” occurs a third time, etc.

State Diagram:

a e

1/1 0/0 0/0 0/0

b

1/0

c

1/0

d

0/1 0/1 1/0 1/1

f

1/1 0/1

State Encoding: a 000 b 001 c 010 d 011 e 100 f 101

6 states  3-bit encoding

001 000 010 011 100 101

3-bit encoding  3 flip-flops

Analysis and Design of Sequential Logic Circuits 6

Input (X) Present State Next State Flip-flop Inputs Output (S) Q2 Q1 Q0 Q2* Q1* Q0* D2 D1 D0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Excitation table using D Flip-flops:

a e

1/1 0/0 0/0 0/0

b

1/0

c

1/0

d

0/1 0/1 1/0 1/1

f

1/1 0/1 001 000 010 011 100 101

Analysis and Design of Sequential Logic Circuits 7

Excitation and output logic functions:

1 2 2 1 1 2 2 1 2 1 1 1 2 1 1 2 2

Q Q Q Q XQ Q X S Q Q X Q Q XQ Q X D Q Q X Q Q Q X Q Q Q X D Q XQ XQ D              

Analysis and Design of Sequential Logic Circuits 8

Circuit Implementation

1 2 2 1 1 2 2 1 2 1 1 1 2 1 1 2 2

Q Q Q Q XQ Q X S Q Q X Q Q XQ Q X D Q Q X Q Q Q X Q Q Q X D Q XQ XQ D              

Analysis and Design of Sequential Logic Circuits 9

Example 3:

Design a sequential comparator circuit that is to determine which of the two multi-bit numbers, A and B, of equal length is larger. Inputs are supplied in MSB first fashion.

00,11/00

00 10 01

X X /01 X X /10

10/10 01/01

Analysis and Design of Sequential Logic Circuits 10

Example 4: Moore Machine



Design a bit-serial odd parity checker: It counts the number of 1’s in a bit- serial input stream and asserts its output when the input stream contains an

• dd number of 1’s.

P.S. Q0 N.S. (Q0*) Out (z) x=0 x=1

even (0) even (0)

• dd

(1)

• dd

(1)

• dd

(1) even (0) 1

reset even

• dd

1 1 1

D x Q z Q   

Using D flip-flops

T x z Q  

Using T flip-flops

Analysis and Design of Sequential Logic Circuits 11

Example: Moore Machine

 A bus controller, that receives requests on separate lines, R0 to R3

from 4 devices to use the bus. It has four outputs, G0 to G3, only one

• f which is 1 (indicating which device is granted control for that clock period). The

lowest number device has the highest priority. A higher priority device can preempt the bus. Assume that, before servicing any pending request, the controller remains idle for one clock period.

 The bus controller has five states:

 A: idle, no device is using the bus  B: device 0 is using the bus  C: device 1 is using the bus  D: device 2 is using the bus  E: device 3 is using the bus

Analysis and Design of Sequential Logic Circuits 12

Moore state machine for the bus controller example.

A

0000

B

1000

C

0100

D

0010

E

0001

Outputs: G0G1G2G3

1XXX 0001 XX0X 1XXX 01XX X1XX 001X 1XXX X0XX 01XX 0000 0XXX 1XXX XXX0 0001 001X 1XXX X1XX XX1X

Inputs: R0R1R2R3

Sequential Circuits 13

Read on your own

Analysis and Design of Sequential Logic Circuits 14

Example – Modulo 3 in Binary

5 7 4 7 9 3 1 3 2 9 2 7 1 3 1 5 1 5 2 9 2 7 2 Modulus  Analogous to Decimal - Use long division

 Take one digit at a time

 Start at the most significant digit

 Calculate remainder  Shift in another digit

 The previous modulus moves to

“tens” position

 Shifted digit gets added

 Calculate remainder  Repeat until all digits are done

Analysis and Design of Sequential Logic Circuits 15

Binary Modulus

 Take one bit at a time (MSB first)  Calculate remainder

 Three possible values – 0,1,2

 Shift in the next bit

 Shifting results in doubling the previous modulus value  New digit gets added to this doubled value

 Perform modulus of the resultant value

      is bit next if ; 2 1 is bit next if ; 1 2 ' m m m

m

3 mod ' 2m m 

Analysis and Design of Sequential Logic Circuits 16

State Table and State Diagram

Present Modulus Next x = 0 x = 1 1 1 2 2 1 2

1 2

1 1 1 Present Modulus Next x = 0 x = 1 00 00 01 01 10 00 10 01 10

Analysis and Design of Sequential Logic Circuits 17

Implementation with T Flip-Flops

Input x Present State Next State Flip-flop Inputs

Q1 Q0 Q1* Q0* T1 T0 1 1 1 1 1 1 1 1

1

1 1

1

1 1

1

1 1

• Q

Q x T Q Q x T      ) ( ) (

1 1 1

Analysis and Design of Sequential Logic Circuits 18

Do it Yourself

1.

Design a Gray code counter using JK flip-flops.

2.

Design a 3 bit up/down counter using T flip-flops. The count direction is determined by input D (D=0 means count down).

3.

Design a sequence detector with one input X and one

• utput Z. The detector should recognize the input

sequence “101”. The detector should keep checking for the appropriate sequence and should not reset to the initial state after it has recognized the sequence.

End of Week 6: Module 30

Thank You

Intro to State Machines 19