System Level Power- Performance Trade-Offs in Embedded Systems - - PowerPoint PPT Presentation

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System Level Power- Performance Trade-Offs in Embedded Systems - - PowerPoint PPT Presentation

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System Level Power- Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory Puttaswamy 1 , Won Choi 1 , Jun Park 1 , Kiran Puttaswamy Kiran , Kyu Kyu- -Won Choi , Jun Cheol Cheol Park ,

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SLIDE 1

October 2002 ISSS 1

1Center for Research on Embedded Systems and Technology

(CREST), http://crest.ece.gatech.edu

2Assistant 3Professor, 1Electrical and Computer Engineering 2Adjunct Assistant Professor, College of Computing

Georgia Institute of Technology, Atlanta, GA USA

4 4Tallin Technical University, Tallin, Estonia

System Level Power- Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory

Kiran Kiran Puttaswamy Puttaswamy1, , Kyu Kyu-

  • Won Choi

Won Choi1, Jun , Jun Cheol Cheol Park Park1, , Vincent J. Mooney Vincent J. Mooney III III1,

1,2,

, Abhijit Abhijit Chatterjee Chatterjee1,

1,3 and

and Peeter Peeter Ellervee Ellervee4 { {kiranp kiranp, , kwchoi kwchoi, , jcpark jcpark, chat, , chat, mooney mooney}@ece.gatech.ed }@ece.gatech.edu u lrv lrv@cc. @cc.ttu ttu. .ee ee

2Hardware/Software

Hardware/Software Codesign Codesign Group, http:// Group, http://codesign codesign. .ece ece. .gatech gatech. .edu edu

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SLIDE 2

October 2002 ISSS 2

Overview

  • Introduction
  • Motivation
  • Contribution
  • Framework
  • Methodology
  • Results
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October 2002 ISSS 3

Introduction

  • Embedded Systems –

essential components of living

  • Constraining Factor: Power
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SLIDE 4

October 2002 ISSS 4

Motivation

  • Limited Battery Capacity
  • Battery Energy Supplying Characteristic

10 mA , 1.5 volts = 1000 hours 100 mA, 1.5 volts = 80 hours

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SLIDE 5

October 2002 ISSS 5

Previous Work

  • Three broad approaches to memory optimization for

power/energy reduction

– Cache optimizations – Memory access reduction (especially of off-chip memory) – Memory sizing/structuring and memory intensive voltage scaling

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October 2002 ISSS 6

Our Contribution

  • Combination of an architectural technique (store

buffer) and a circuit level technique (voltage and frequency scaling) to realize savings in both power and energy in an embedded system composed of an ARM- like processor chip plus a separate memory chip

  • System savings in power from 28% to 36%
  • System savings in energy from 13% to 35%
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October 2002 ISSS 7

Computation Part of an Embedded System

CPU Data cache Instruction cache Off-Chip Memory

64 96 32 32

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October 2002 ISSS 8

Power Models

  • Verilog RTL model for processor (excluding caches)
  • Compaq Personal Server PCB Board called “Skiff”
  • Analytical memory model for caches and off-chip

memory

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October 2002 ISSS 9

Framework

Benchmark Programs ( c ) Off-Chip Memory Power Model Toggle Rate Generation MARS Simulator VHX Translation Processor Core Power Model Off-chip Bus Power Model System Level Power

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October 2002 ISSS 10

Wither the power?

  • Computation in system

– MARS processor (U. Michigan, www.eecs.umich.edu/~jringenb/power)

  • ~30K lines Verilog

– synthesized using TSMC .25u std. cell lib. from LEDA Systems

  • 4KB Icache, 4KB Dcache

– 0.5MB SRAM memory chip (L2)

  • Approximately 50% of the power consumed by processor chip

(excluding I/O pads and drivers)

  • 50% of the power consumed to drive L2 memory: the 0.5MB

memory chip + PCB bus + I/O pads/drivers

  • => reduce power to drive L2 memory by 60%, system power

reduced 30%

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October 2002 ISSS 11

3.3 V -> 2V, SRAM delay doubles, power reduces up to 66% Use TSMC 0.25 u

  • tech. param. from

MOSIS

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SLIDE 12

October 2002 ISSS 12

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October 2002 ISSS 13

Embedded System

CPU Data cache Instruction cache Off-Chip Memory

64 96 32 32

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October 2002 ISSS 14

Embedded System (with Store Buffer)

CPU Data cache Instruction cache Off-Chip Memory

64 96 32 32 Store buffer

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October 2002 ISSS 15

Methodology

  • Voltage/frequency scaling of L2 memory accesses
  • Store buffer technique
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October 2002 ISSS 16

Voltage/Frequency Scaling

Processor Off-chip Memory Off-chip Buses 3.3 Volts, 100 Mhz 2.75 Volts, 100 Mhz 3.3 V, 100 Mhz 2 Volts, 50 Mhz 2 Volts, 50 Mhz

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October 2002 ISSS 17

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October 2002 ISSS 18

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October 2002 ISSS 19

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October 2002 ISSS 20

Conclusion

  • Reduction in both power and energy

– For an ARM-like processor chip plus a separate memory chip: – System savings in power from 28% to 36% – System savings in energy from 13% to 35% – Increase in execution time from 1% to 29%

  • Possible technique for power modulation

by user/application