System a em arch chitect ecture f e for n net etwork-attach - - PowerPoint PPT Presentation

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Feb 12, 2024 169 likes •223 views

System a em arch chitect ecture f e for n net etwork-attach ached ed Research | Zurich FPGAs i in t the C e Clou oud u using p par artial al r rec econfj fjguration Burkhard Ringlein, Francois Abel, Alexander Ditter, Beat

SLIDE 1

Research | Zurich

64/chassis 1024/rack

Standalone network-attached FPGAs over TCP/IP/Ethernet

10 Tb/s full-duplex

Plentiful/DC

System a em arch chitect ecture f e for n net etwork-attach ached ed FPGAs i in t the C e Clou

ud u

using p par artial al r rec econfj fjguration

Burkhard Ringlein, Francois Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, and Dietmar Fey

SLIDE 2

Research | Zurich

System Architecture: Requirements and Proposal

1) Standa dalon

ne FPGAs must control

themselves 2) Abstract the physical FPGA 3) No disclose of sources required 4) Guarantee integr grity of the DC 5) Build clusters dynamically 6) Reuse / Integrate with existing DC services

SLIDE 3

Research | Zurich

System Architecture: Requirements and Proposal

1) TCP/IP and d REST (Representational State Transfer)

have proven to
sca

cale

are hardw

rdware re agn gnos

stic

2) FPGA must reconfjgure itself 3) Separation of privileges and network interfaces within the FPGA → using partial reconfjguration via a RESTful API based on TCP/IP 1) Standa dalon

ne FPGAs must control

themselves 2) Abstract the physical FPGA 3) No disclose of sources required 4) Guarantee integr grity of the DC 5) Build clusters dynamically 6) Reuse / Integrate with existing DC services

SLIDE 4

Research | Zurich

System Architecture: Divide and Conquer

1 2 3

Three le

levels ls of

f Ma

Management: t: 1) Data Center 2) per Sled/Chassis 3) per FPGA

Results

ts: 1) < 2% of a Xilinx Kintex 2) deployment time independent of cluster/application size 3) single application bit-stream for “zillions” of FPGA nodes 4) fast confjguration

SLIDE 5

Research | Zurich

System Architecture: Divide and Conquer

1 2 3

Three le

levels ls of

f Ma

Management: t: 1) Data Center 2) per Sled/Chassis 3) per FPGA

Results

ts: 1) < 2% of a Xilinx Kintex 2) deployment time independent of cluster/application size 3) single application bit-stream for “zillions” of FPGA nodes 4) fast confjguration

System a em arch chitect ecture f e for n net etwork-attach - - PowerPoint PPT Presentation

64/chassis 1024/rack

Standalone network-attached FPGAs over TCP/IP/Ethernet

10 Tb/s full-duplex

Plentiful/DC

System a em arch chitect ecture f e for n net etwork-attach ached ed FPGAs i in t the C e Clou

using p par artial al r rec econfj fjguration

Burkhard Ringlein, Francois Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, and Dietmar Fey

System Architecture: Requirements and Proposal

1) Standa dalon

themselves 2) Abstract the physical FPGA 3) No disclose of sources required 4) Guarantee integr grity of the DC 5) Build clusters dynamically 6) Reuse / Integrate with existing DC services

System Architecture: Requirements and Proposal

1) TCP/IP and d REST (Representational State Transfer)

cale

rdware re agn gnos

2) FPGA must reconfjgure itself 3) Separation of privileges and network interfaces within the FPGA → using partial reconfjguration via a RESTful API based on TCP/IP 1) Standa dalon

themselves 2) Abstract the physical FPGA 3) No disclose of sources required 4) Guarantee integr grity of the DC 5) Build clusters dynamically 6) Reuse / Integrate with existing DC services

System Architecture: Divide and Conquer

1 2 3

levels ls of

Management: t: 1) Data Center 2) per Sled/Chassis 3) per FPGA

ts: 1) < 2% of a Xilinx Kintex 2) deployment time independent of cluster/application size 3) single application bit-stream for “zillions” of FPGA nodes 4) fast confjguration

System Architecture: Divide and Conquer

1 2 3

levels ls of

Management: t: 1) Data Center 2) per Sled/Chassis 3) per FPGA

ts: 1) < 2% of a Xilinx Kintex 2) deployment time independent of cluster/application size 3) single application bit-stream for “zillions” of FPGA nodes 4) fast confjguration

Thank you…

ngl@zurich.ibm.com zurich.ibm.com/cci/cloudFPGA/