Synergistic Modeling & Optimization for Physical and Electrical - - PowerPoint PPT Presentation
Synergistic Modeling & Optimization for Physical and Electrical DFM David Z. Pan Dept. of Electrical and Computer Engineering The University of Texas at Austin dpan@ece.utexas.edu http://www.cerc.utexas.edu/utda Sponsored by NSF, SRC,
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Sponsored by NSF, SRC, Fujitsu, IBM, Intel, Qualcomm, Sun, KLA-Tencor
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Background & Motivation DFM Modeling, OPC and Characterizations
DFM Optimizations
Conclusions
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227nm @ 0.85NA 136nm 114nm 91nm 68nm
OAI better OAI + PSM Add biasing Add scatter bars “Full” OPC
68nm (Source: ASML)
OPC: optical proximity correction; OAI: Off-axis illumination PSM: phase shift mask
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Industry stuck with 193nm lithography (in the next 5
» EUVL, E-Beam, nano-imprint… » 157nm declared dead Very deep sub-wavelength (VDSW) + very deep
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Litho CMP Random defects
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Modeling, extraction and characterization Insert proper metrics into the main design flow
(litho, CMP, etc)
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Background & Motivation DFM Modeling, OPC and Characterizations
DFM Optimizations
Conclusions
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To guide lithography aware physical design, fast yet
Process-oriented vs. Design-oriented Two key stages in litho-model (in a simplified view)
› Optical system: will generate aerial image from mask › Resist system: photoresist and patterning inside the wafer
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Hopkins image equation is generic for optical system
› UI: Image complex amplitude › F: mask transmission function › K: optical system transmission function
1 1 1 1
I
+∞ +∞ −∞ −∞
' ' ' ' 1 1 ' ' ' ' 1 1 1 1
I
∗ ∗
› Image intensity function for partial coherent system
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Directly using Hopkins equation can be extremely slow Kernel decomposition into the sum of a small number of
( )
1 2 1
x y
P j i i j A
,
− = ∈
(a) (b)
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Store convolution table for rectangles w.r.t the top-right
Support region is pretty small Design-oriented fast simulation
R3 R R1 R2 R4
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From the aerial image => printed image (resist model) Example: simple threshold model (e.g., 0.3Imax) to decide
› And many more accurate models
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The printed image is subject to process variations
defocus
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Focus variation: defocus aerial image expansion
Dosage variation: equivalent threshold variation in the
Threshold Bias Resist Model
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EPE under process variations
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Given certain focus and dosage variations, e.g.
Concepts are generic to other “raw” distributions
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Key Idea: Derive/Extract variational EPE from
Run time only 2-3x compared to nominal process,
Can be used to guide true PV aware OPC (PV-
[Yu et al, DAC’06]
US Patent Pending (supported by SRC)
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I-V curves with Vgs = 0.4, 0.8, 1.2V NMOS Leakage with Vds = 1.2V
Electrical characterizations of a 65nm inverter PV-OPC is able to meet design intent under
3x difference in leakage!
PV-OPC Ideal mask Conventional OPC
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Layout-dependent non-rectangular gate
A novel sparse-matrix formulation for SSTA
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½ adder example: a b c d e f g
a b c1 c2 d1 d2 e1 e2 f1 f2 1 1 1 1 1 1 g 1 1 1 1 1 1 1 1
All i/p – o/p, latch-latch paths are represented Each column is an input pin Each row is a complete path A 1 means input pin is on this path Incidence matrix is quite sparse!
Path delays can be written in p = A d.
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By linear regression, express gate delay as a
Linear regression (≠ Linear models), e.g.:
½ – …
Collect all regression terms into one vector z
Regression term z1 Regression term z2
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Delay for gate k: dk = ckT zk
Expanding for all gates/arcs:
=> d = C z a b c d e f g
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Equation for all path delays given by:
Values of z determined by technology settings
Path delays corresponding to these n samples:
Fast Monte-Carlo SSTA in sparse-matrix form:
Handle slope propagation nicely (a new C’ matrix) Method implemented/used by industry.
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Background & Motivation DFM Modeling, OPC and Characterizations
DFM Optimizations
Conclusions
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Blockage
Global Routing Track Routing Detailed Routing Placement Routing Manufacturing Routing
a a a a b b c c c d d
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[Courtesy IBS]
Critical Area CMP Lithography
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CMP variation optimization
› Minimum effective window (20x20μm2) and global effect › Global routing plans approximate routing density
Critical area optimization
› Adjacent parallel wires contribute majority of critical area. › Track router has good flexibility with wire ordering/spacing/sizing.
Lithography optimization
› Effective windows (1-2μm2 ) are small › Detailed router performs localized connection between pins/wires.
Global Routing Track Routing Detailed Routing
CMP variation optimization Critical area minimization Lithography enhancement
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More & more metal layers need RETs Rule vs. model based approach Rules -
How about directly link litho-models with routing?
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First work to truly link lithography modeling with
Introduce the concept of Litho- Hotspot Maps Fast lithography simulation to generate LHM
Post-routing optimizations to reduce hotspots
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Initial routing (after design closure) 40% EPE reduction (much less litho hot spots) [Mitra et al, DAC’05]
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Lithography hotspot is a generic concept Other metrics may be used: Not just EPE
We are developing a new correct-by-construction
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Lithography interact with CMP
CMP-Aware Routing
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In general, more uniform wire density
› Better CMP topography variations
Wire density will affect timing too
› Lower wire density => less resistance (higher thickness) › Lower wire density => less capacitance
Wire density: a unified metric for CMP and Timing
Wire density vs. congestion driven GR
› Though correlated, indeed different during global routing › Density: wires inside global routing cells › Congestion: wires crossing the boundaries of global routing cells
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Incremental Box
› From most congested regions Progressive ILP Adaptive maze routing PostRouting › Negotiation-based approach
DAC’06 BPA Candidate 2nd place (in 3D) ISPD07
US Patent filed by SRC Open Source Released
Global routing cell (G-cell)
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Global Routing
Wire Density Cu Thickness
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Density vs Thickness 0.8 0.85 0.9 0.95 1
24%28%32%36%40%44%48%52%56%60%64%68%72%76%80%
Metal Density Normalized Thickness Average Dummy Density Distribution (TILE=20um) 0% 10% 20% 30% 40% 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% Wire Density Dummy Fill Density
Calculate Wire Density Required Dummy Density (From Lookup Table) Metal Density = Wire Density + Dummy Density Thickness = A* (1- Metal Density2/B) /B)
[Cho et al, ICCAD’06]
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Global Routing W i r e D e n s i t y Cu Thickness Dummy Fill Density From Lookup Table Metal Density = Wire Density+ Dummy Fill Density Cu Thickness
Predictive CMP Model for Global Routing
Predictive CMP Model guides global router
› More uniform wire distribution › Consider metal blockages (power/ground rail, IPs)
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0.84 0.86 0.88 0.9 0.92 0.94 0.96 0.98 1 Normalized Variation ibm01 ibm02 ibm03 ibm04 ibm05 ibm06 ibm07 ibm08 ibm09 ibm10
BoxRouter Wire density
On average 7.5%
Up to 10.1% reduction
0.84 0.86 0.88 0.9 0.92 0.94 0.96 0.98 1 Normalized timing ibm01 ibm03 ibm05 ibm07 ibm09
BoxRouter Wire density
CMP variation
On average 7%
Up to 10% reduction
Timing [Cho et al, ICCAD’06]
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Random defect can cause open/short defect
› Wire planning for critical area reduction
Defect size distribution
› Chance of getting larger defect decreases rapidly [TCAD85]
Concurrent optimization for open/short defect
› Larger wire width for open, but larger spacing for short defect › Limited chip area
Critical area due to open defect
› Reduce defect size › Increase wire width
Critical area due to short defect
› Reduce defect size › Increase wire spacing
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TROY is the first yield-driven track router
» Preference-aware Minimum Hamiltonian Path
» Second-order conic programming (SOCP) » global optimal in nearly linear time Result is very promising
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Defect size distribution r =3 Critical are due to open defect Critical are due to short defect Probability of failure (POF) for open/short defects Approximated POF
POFs for open/shorts are convex functions
› Global optimal can be found, but POF is complicated. › Approximated POF is also convex, but easy enough to enable SOCP.
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Integer nonlinear programming
› Extremely hard to solve › Integer variable for the wire order oij (above/below relationship)
POF for
POF for short Min/max width and spacing constraints, and desired locations
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Integer nonlinear programming
Second order conic programming (SOCP)
SOCP: Global optimal solution in nearly linear time
Solved by finding minimum Hamiltonian path
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200 400 600 800 1000 1200 1400 Yield loss out of 10K
ibm01 ibm02 ibm03 ibm04 ibm05 ibm06 ibm07 ibm08 ibm09 ibm10
TCAD01 TROY TROY.D Greedy algorithm [Tseng TCAD01] TROY: continuous wire width
[Cho et al, DAC’07]
Monte-Carlo simulation with 10K defects On average 18 % reduction in yield loss, up to 30% Discretization only loses 2%
TROY.D: discrete wire width
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The reality is of course, MORE COMPLICATED Need to consider the interactions between CMP,
Global Routing Track Routing Detailed Routing
CMP variation optimization Critical area minimization Lithography enhancement Redundant via enhancement
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Variation reduction => variation tolerance Temperature aware clock opt. [ICCAD’05] Clock tree link insertion [Rajaram+, ISPD’05,
Meshworks: clock mesh planning/synthesis
Mesh -> remove links? CTS -> add links
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193nm lithography will still be the dominant chip
Synergistic modeling & optimization needed in a
Current works just scratch the surface Need much closer collaborations than ever
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Sponsorship by NSF, SRC (core + custom
PhD students at UTDA: Minsik Cho, Joydeep
Collaborations/discussions with Dr. Chris Mack,