Symbol Timing Synchronization ELEC 433 - Spring 2013 Michael Wu - - PowerPoint PPT Presentation

Symbol Timing Synchronization

ELEC 433 - Spring 2013 Michael Wu & Evan Everett

Question from Lab 6

• 2. Introduce a variable delay between the upconverter and downconverter, with the delay

value selectable in your software that runs on the PPC. The addressable shift register block will be useful here. Observe the effect on the received constellations.

Why?

Question from Lab 6

T 2T 3T

• T
• 2T
• 3T

t

Intersymbol Interference (ISI)

S1 S2 S3 S4

One way to visualize the effect

Matched Filter

Transmitted Symbol

The “correct” delay yielded good results

S1 S2 S3 S4

One way to visualize the effect

Matched Filter

Transmitted Symbol

} Poor Synchronization ⇒ S1 and S2 Interfere (ISI) Think of this case as what would happen if the receiver turns on a little too late

S1 S2 S3 S4

One way to visualize the effect

Matched Filter

Transmitted Symbol

It’s even worse than just an initial offset... what if the TX sampling clock is a slightly different frequency than the RX? The windows drift

Our Mission

Can we track and compensate for this drift?

Symbol Timing Synchronization

• Generally can’t change hardware clock
• Frequency & phase fixed
• Need to synchronize using only signal processing
• Basic approach analogous to carrier recovery
• Timing error detector
• Loop filter
• Timing error correction

Receive Chain

Down- converter Decimating Matched Filter Phase Error Detector Loop Filter Received Signal

Carrier Offset Recovery

Receive Chain

Down- converter Decimating Matched Filter Timing Error Detector Loop Filter Received Signal

Symbol Timing Synchronization

Delay Tracker Variable Delay

Down- converter Decimating Matched Filter Timing Error Detector Loop Filter Received Signal Delay Tracker Variable Delay

Timing Error Detector

• Assume an alternating I or Q
• Sampling early yields a positive

slope in the bandlimited waveform

• Sampling late yields a negative

slope in the bandlimited waveform

• Sampling at the correct point yields

a slope of zero in the bandlimited waveform

• For positive I or Q
• For negative I or Q, the slopes are

negated

Matched Filter Output

Timing Error Detector

• Use a filter with h[n] = d(hMF[n])
• Called a derivative matched filter
• Hint: d(h[n]) ≈ conv(h[n],[1 0 -1])
• Output should be zero at correct instant
• Output is max/min at worst sampling instant

Downconverted I MF sign terror dMF

Timing Error Detector

Timing Error Detector

• What if I or Q isn’t alternating positive and negative?
• correct sample, but non-zero slope

Timing Error Detector

• Our input data is random, should have enough level

transitions

• We can just let the loop filter average out the errors

in the timing error calculation

• There are a few ways to deal with insufficient level

transitions

• Manchester codes and 8b/10b encoding are

techniques used in wireline communications to increase level transitions

• Scrambling data (like 802.11) increases level transitions

Loop Filter

Down- converter Decimating Matched Filter Timing Error Detector Loop Filter Received Signal Delay Tracker Variable Delay

Loop Filter

• Same 2nd order filter structure as carrier recovery
• Different coefficients

K_P K_I terror Accumulator terror-filt K

Delay Tracker

Down- converter Decimating Matched Filter Timing Error Detector Loop Filter Received Signal Delay Tracker Variable Delay

Delay Tracker

• Computes required delay to correct timing
• M is upsampling rate
• Error input comes from loop filter
• Runs at fast clock (M*symbol rate)

terror-filt ±1 Limited Accumulator (2/M) 0...(M-1) Counter Rollover Detector Reg en d Delay

Example 1 - Perfect Sampling

a b b a

} 2/M

1 M-1

terror-filt ±1 Limited Accumulator (2/M) 0...(M-1) Counter Rollover Detector Reg en d Delay

Example 2 - Late Sampling

d a b b a

}2/M + d

1 M-1

} 2/M

(If the correction fixed the problem)

terror-filt ±1 Limited Accumulator (2/M) 0...(M-1) Counter Rollover Detector Reg en d Delay

Example 3 - Early Sampling

a b b a

} 2/M - d

1

• d

M-1

} 2/M

(If the correction fixed the problem)

terror-filt ±1 Limited Accumulator (2/M) 0...(M-1) Counter Rollover Detector Reg en d Delay

Variable Delay

Down- converter Decimating Matched Filter Timing Error Detector Loop Filter Received Signal Delay Tracker Variable Delay

• Output of delay tracker computes the required delay
• Up to you to implement the variable delay
• Hint: addressable shift register (ASR)

Summary

• Test the design in simulation for a variety of starting

delays between TX and RX.

• No hardware build this week

Down- converter Decimating Matched Filter Timing Error Detector Loop Filter Received Signal Delay Tracker Variable Delay