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Study of efficiency and noise of fine pitch planar pixel detector - - PowerPoint PPT Presentation

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Study of efficiency and noise of fine pitch planar pixel detector for ATLAS ITk upgrade Koji Nakamura (KEK) On behalf of ATLAS Japan Pixel group and Hamamatsu Photonics K.K. 13th Dec 2019 Pixe 2018 1 Introduction High Luminosity LHC

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SLIDE 1

Study of efficiency and noise of fine pitch planar pixel detector for ATLAS ITk upgrade

Koji Nakamura (KEK) On behalf of ATLAS Japan Pixel group and Hamamatsu Photonics K.K.

13th Dec 2019 1 Pixe 2018

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SLIDE 2

Introduction

13th Dec 2019 Pixe 2018 2

  • High Luminosity LHC (HL-LHC)

– Start around 2026- with new crab cavity in the interaction region. – Target : 𝒕=14TeV L=5x1034 𝑴𝒆𝒖=3000fb-1 – Physics program focus the precise measurement of the Higgs coupling (e.g. Yτ, Yb and λHHH) and BSM searches.

  • Tracking detector is key element

– To keep B/τ-tagging performance up to μ=200 pileup in an event. – Mitigation for the pileup effect for MET calculation can be done by tracking from primary vertex.

  • Development of middle-outer pixel layer

– Planar type Pixel detector (For ATLAS phase II upgrade : ITK pixel) – n+-in-p sensor with Pixel size : 50um x 50um (or 25um x 100um) – Radiation tolerance : up to 3x1015 neq/cm2

Sensor performance of 50um x 50um planar pixel detector is presented.

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SLIDE 3

Bias structure and efficiency loss

  • For n+-in-p sensor, negative

bias to backside and ground at all pixels.

  • Need to set all pixels to ground

potential for testing I-V property before Bump bonding. (Bias structure)

– Bias rail & bias resistor (BR) – Punch through (PT)

  • Two important feature

– Higher noise observed for pixels with BR structure. – Typical Efficiency drop at under bias structure observed.

13th Dec 2019 Pixe 2018 3

B

n+

Bias-rail Poly-Si P-stop Bump e- e- e- h h h Al SiO2

  • V

P-bulk

Typical efficiency drop

Bias rail & bias resistor Punch through

n+

  • K. Nakamura et al 2015 JINST 10 C06008
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SLIDE 4

Available Read out ASICs

  • For sensor performance evaluation, used FE-I4, FE65p2 and RD53A.
  • FE65p2 is small prototype ASIC for RD53A and have lower noise

than FE-I4.

13th Dec 2019 Pixe 2018 4

FE-I4 (2012) FE65p2 (2016) RD53A (Nov. 2017) ASIC demention CMOS process 130nm 65nm 65nm Pixel size 50um x 250um (25um x 500um) 50um x 50um (25um x 100um) 50um x 50um (25um x 100um) Pixel matrix 336 x 80 64 x 64 400 x 192 Max data output rate 160Mbps 160Mbps 1.28Gbps x 4 stable threshold (typical threshold) ~1500 e- (2000-3000 e-) 500 e- (700 e-) 500 e- 17mm 20mm 4mm 3mm 11.8mm 20mm

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SLIDE 5

Available Read out ASICs

13th Dec 2019 Pixe 2018 5

FE-I4 (2012) FE65p2 (2016) RD53A (Nov. 2017) ASIC demention CMOS process 130nm 65nm 65nm Pixel size 50um x 250um (25um x 500um) 50um x 50um (25um x 100um) 50um x 50um (25um x 100um) Pixel matrix 336 x 80 64 x 64 400 x 192 Max data output rate 160Mbps 160Mbps 1.28Gbps x 4 stable threshold (typical threshold) ~1500 e- (2000-3000 e-) 500 e- (700 e-) 500 e- 17mm 20mm 4mm 3mm 11.8mm 20mm

  • For sensor performance evaluation, used FE-I4, FE65p2 and RD53A.
  • FE65p2 is small prototype ASIC for RD53A and have lower noise

than FE-I4.

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SLIDE 6

p+ p+ n+ P-bulk

6th sensor mask by HPK/KEK

13th Dec 2019 Pixe 2018 6

FE-I4/FE65p2 compatible RD53A compatible Comment n+ size (gap) 28um(22um) 39.5(10.5um)/31.5um(18.5um) To improve efficiency SiO2 over p-stop 400nm 400nm / 800nm To improve efficiency Poly-si resistivity 560kΩ 2.0MΩ (660KΩ-6MΩ) Larger resistivity Al size (gap) 39.5um(10.5um) 45.5um(4.5um) / small Large/small Cintpix SiO2 on Poly-Si 100nm 100nm / 500nm Smaller Cpolysi-Al FE-I4/FE65p2 type RD53A type

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SLIDE 7

6th sensor mask by HPK/KEK

13th Dec 2019 Pixe 2018 7

Single chip sensor 32 (4type x8) sensor / wafer double chip sensor 10 (2type x 5) sensor / wafer Reticle 44mm HPK 6th mask

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SLIDE 8

Irradiation Facility in Japan

13th Dec 2019 Pixe 2018 8

  • CYRIC@Tohoku Univ. is a irradiation facility with 70MeV proton beam (~1μA).

– This allows 5-6 pixel module with back Al plain at the same time(3% E loss/pixel). – Operated at -15℃ temprature with dry N2 gas.

  • Programmable X-Y stage and “push-pull” mechanism are implemented to the

machine.

– choose one or a few target samples in max 15 pre-installed samples.

  • Scanning over full pixel range during irradiation.
  • Actual Fluence difference relative to the target fluence is within ~10%.

Target Sample Evacuated Samples

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SLIDE 9

Testbeam at CERN SPS H6A/B

  • To evaluate efficiency in pixel, performed testbeam

before/after irradiation.

– CERN H6 beam line

  • 120GeV pion beam
  • 7 testbeams in 2016-2018 at CERN (and Fermilab)

– Typical CERN TB

  • 6 layer of telescope
  • 3-5um pointing resolution
  • DUTs are in the cooling box

13th Dec 2019 Pixe 2018 9

tel1 tel2 tel3 tel4 tel5 Reference HPK RD53a tel0 Irrad module

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SLIDE 10

p+ p+ n+ P-bulk

Noise increase by Biasing structure

  • Higher noise in the pixel with BR observed

– Depends on the FE circuit

  • FE65p2 : 90e RD53A : 215e effect
  • Under investigation with chip designer.

– Depends on resistivity of poly-si and capacitance between poly-si/Al

13th Dec 2019 Pixe 2018 10

Large N+ Bias -20V ~36e ~100e ~80e ~230e No BR w/ BR No BR w/ BR First 65nm CMOS analog FE testing chip (FE65p2) 400x192 pix prototype (RD53A) Poly-si Al

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SLIDE 11

13th Dec 2019 Pixe 2018 11

p+ p+ n+ P-bulk p+ p+ n+ P-bulk Small Al STD Al

Noise measurement for RD53A module

– Compared top Al size

  • Smaller Al have smaller noise

Affected by Capacitance between Poly-si and Al

Bias -20V No BR w/ BR

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SLIDE 12

13th Dec 2019 Pixe 2018 12

p+ p+ n+ P-bulk

Noise measurement for RD53A module

  • SiO2 thickness comparison

– Compared SiO2 thickness btw Poly-si and Al

  • Thicker SiO2 have smaller noise

– Compared SiO2 thickness btw Poly-si and n+

  • No visible difference

Affected by Capacitance between Poly-si and Al

SiO2 btw Poly-si and Al SiO2 btw Poly-si and n+ Bias -20V No BR w/ BR

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SLIDE 13

p+ p+ n+ P-bulk

  • Poly-si resistivity comparison

– Compare 0.67MΩ, 2MΩ, 6MΩ

  • Larger resistivity have smaller noise

13th Dec 2019 Pixe 2018 13

Noise measurement for RD53A module

Highly affected by poli-si resistivity

No bias supplied No BR w/ BR Increase resistivity

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SLIDE 14

13th Dec 2019 Pixe 2018 14

p+ p+ n+ P-bulk

Noise measurement for RD53A module

  • Noise is affected by poly-si resistivity and capacitor btw poly-

si and Al

– Tested Smaller top Al & thicker SiO2 & higher poly-si resistivity

  • Indeed the condition is the best, resistivity is highest contribution

170e 70e +150e by quadrature

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SLIDE 15

Poly-si resistivity after Irradiation

  • Measurement done using TEG with the same

poly-si resister pattern.

– Compared various sheet resister target wafers. – Tested 0.6MΩ, 2MΩ, 4MΩ, 6MΩ – Can achieve >5MΩ

13th Dec 2019 Pixe 2018 15

2 4 6 8 10 12 14 16 5E+15 1E+16 1.5E+16 1 1 5 5 6 6 7 7

Type7 6MΩ target Type7 6MΩ target Type6 4MΩ target Type6 4MΩ target Type1 2MΩ target Type1 2MΩ target Type5 0.6MΩ target Type5 0.6MΩ target Fluence [neq/cm2] Resistivity (MΩ)

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SLIDE 16

p+ p+ n+ P-bulk

Noise measurement after irradiation

13th Dec 2019 Pixe 2018 16

  • For default type :

– Compared before and after irradiation

  • Smaller noise after irradiation due to high

resistivity after 3x1015neq/cm2 irradiation

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SLIDE 17

Efficiency loss due to charge sharing

  • Charge sharing effect

– After proton irradiation, about 8k electron-hole pair created by ionizing loss of MIP particle in 150um thick sensor. – At the corner of pixel, charge is splitting to 4 pixels (2ke each). – Efficiency loss occur if the comparator threshold

  • f readout ASIC is >2ke.

– In case of 50um x 250um pixel efficiency loss are ~1% to overall efficiency @ 2400e.

  • Finer pixel size (50um x 50um)

– expected to 5 times larger effect than 50um x 250um pixels. – Lower noise ASICs than FE-I4 helped to improve efficiency i.e. FE65p2 and/or RD53A

  • No visible efficiency drop for FE65p2 but there was

issue for the absolute value of efficiency

13th Dec 2019 Pixe 2018 17

e- h e- h e- h e- h 8ke 2ke 2ke 2ke 2ke Type2 : w/ BR Structure(600V)

K.Nakamur akamura et. al. NIM M A: doi.org/10. 0.10 1016/ 16/j.ni nima. ma.20 2018. 18.09 09.015 15

Tested RD53A modules

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SLIDE 18

Efficiency results (non-irrad)

  • Results with 2000e thresholds.

– Efficiency is over 99% for all types.

  • Still checking the proper mask has been applied.
  • No visible efficiency drop at the corner of pixel.

– 20V is already enough voltage to have 99% efficiency.

13th Dec 2019 Pixe 2018 18

Overall efficiency Default type Bias -100V

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SLIDE 19

p+ p+ n+ P-bulk p+ p+ n+ P-bulk

Efficiency result (irrad 3x1015neq/cm2)

  • Efficiency results of HV scan 200-800V have been evaluated.

– Analyzed both 1500e and 2400e threshold data for different types. – All types have over 98% efficiency at 600V.

  • 1500e threshold results have over 99% efficiency.
  • Small n+ w/ BR have low efficiency at 200V

13th Dec 2019 Pixe 2018 19

Small n+ w/ BR Large n+ w/ BR w/o BR th2400 th1500

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SLIDE 20

Conclusion and plan

13th Dec 2019 Pixe 2018 20

  • Conclusion

– Develop optimized sensor structure for HL-LHC ATLAS phase-II upgrade. – New sensor mask compatible to the RD53A ASIC has been developed. – Pixel with Biasing structure have larger noise.

  • Larger resistivity and smaller capacitance btw poly-si/Al improve this.
  • Best design have 150e increase by BR.

– Efficiency results

  • Non-irrad sample have over 99% efficiency
  • Irrad module have over 98 % efficiency for both w/ and w/o BR.
  • Plan

– Understanding the source of noise with Spice Simulation of RD53A ASIC with resister between input pads. – Quad sensor production as the final design of ATLAS ITk modules.

Satisfied ATLAS ITK-pixel requirements

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SLIDE 21

Contributer

  • Koji Nakamura, Yoichi Ikegami, Kazunori Hanagaki, Manabu

Togawa, Yoshinobu Unno (KEK)

  • Kazuki Uchiyama, Daigo Harada, Kyoji Onaru, Kazuhiko Hara

(Tsukuba)

  • Yuto Nakamura, Osamu Jinnouchi (Tokyo Tech.)
  • Shintaro Kamada, Yohei Abo, Kazuhisa Yamamura, Hirokazu

Yamamoto (HPK)

13th Dec 2019 Pixe 2018 21

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SLIDE 22

backup

13th Dec 2019 Pixe 2018 22

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SLIDE 23

p+ p+ n+ P-bulk

Noise measurement for RD53A module

  • Check only DIFF FE

– Measured by threshold scan by YARR – -20V bias supplied. – Compered with and w/o Bias structure

  • No BR~ 80e, With BR~ 230e (increase 215e)

– Compared n+ size

  • No major difference for both w/ and w/o BR.

13th Dec 2019 Pixe 2018 23

No BR With BR p+ p+ n+ P-bulk STD N+ Large N+ Bias -20V No BR w/ BR

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SLIDE 24

Equivalent circuit

13th Dec 2019 Pixe 2018 24

p+ p+ n+ P-bulk

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SLIDE 25

Equivalent circuit

13th Dec 2019 Pixe 2018 25

p+ p+ n+ P-bulk

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SLIDE 26

Location of efficiency drop

  • In case of small n+ size, Efficiency drop at the corner

which wide bias rail located. (3x1015 irrad @800V)

13th Dec 2019 Pixe 2018 26

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SLIDE 27

Efficiency loss per pixel (FE-I4)

13th Dec 2019 Pixe 2018 27

Type5 : No BR Type6 : 25x100um Type6 : BR with offset Type5 : No BR (low th) Type6 : 25x100um (low th) Type1 : BR no offset Non-negligible charge sharing effect Lower threshold seems help a lot. 2% Efficiency loss was well below 1% for 50x250um pixels… But… 50x50um pixles Type6 : BR to GND 5%

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SLIDE 28

Results : irrad 3x1015neq/cm2 (FE65p2)

  • Projection of In-pixel efficiency

– For both 25x100um and 50x50um pixel size, efficiency loss at the pixel boundary at 600V are consistent to Zero. For 25x100um w/ bias str at 400V(left blue) Eloss=0.90±0.05%. – 200V 25x100um w/ bias str is also shown(left red).

13th Dec 2019 Pixe 2018 28

25x100 um 50x50 um Eloss=0.9+/-0.0５(%) Eloss=4.0+/-0.1(%) Efficiency loss is less than 1% @ 400V

Normalized Normalized

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SLIDE 29

Flip chipping development

13th Dec 2019 Pixe 2018 29

  • Development of Lead-free(SnAg)

Bumpbonding (Since 2012)

1. No Flux used

  • confirmed flux improve connection, though

2. No backside compensation

  • Improvement of Vacuum chuck jig to hold and

flatten the ASIC/Sensor…(jig size ~ FE-I4 area)

3. Special UBM (key element: cannot tell much…)

  • Simple Ni/Au UBM was not 100% yield …

4. Hydrogen plasma reflow to remove surface

  • xide
  • Thin sensor/Thin ASIC : 150um/150um

– Established Bumpbonding method in the beginning of 2016. – Quite stable quality for both single and four

  • ASICs. 100% yield for last one year (>100

chips are bumpbonded.)

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SLIDE 30

Optimization of Bias structure

  • Very first module HPK produced have critical

efficiency loss at the inter pixel region.

13th Dec 2019 Pixe 2018 30

  • K. Nakamura et al 2015 JINST 10 C06008

B

n+

Bias-rail Poly-Si P-stop Bump e- e- e- h h h

p Bulk

Al SiO2

  • V

Typical efficiency drop

Bias-rail Poly-Si SiO2

  • V

No significant loss

e- h e- h e- h e- h 8ke 2ke 2ke 2ke 2ke

  • 2 issues

– Charge sharing – Potential of Bias-rail

  • Improvement :

– Move Bias-rail position to inside of n+ implant.

Irrad (3x1015neq/cm2)

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SLIDE 31

Optimization of Bias structure

  • Achieved great

improvement!!

13th Dec 2019 Pixe 2018 31

B

n+

Bias-rail Poly-Si P-stop Bump e- e- e- h h h

p Bulk

Al SiO2

  • V

Typical efficiency drop

Bias-rail Poly-Si SiO2

  • V

No significant loss

  • K. Nakamura et al 2015 JINST 10 C06008

Irrad (3x1015neq/cm2) Big improvement

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SLIDE 32

Charge sharing v.s. threshold

13th Dec 2019 Pixe 2018 32

2016Aug Th3000e HV=1000V 2016Nov Th2200e HV=917V Th3000e – Th2200e 2016Aug Target : th3000e Bias rail : float 2016Nov Target : th2200e Bias rail : float

  • Lower threshold simply

recover efficiency !!

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SLIDE 33

Bias rail to GND v.s. floating

13th Dec 2019 Pixe 2018 33

2016Nov Target : th3000e Bias rail : GND Threshold~2300e 2016Aug Target : th3000e Bias rail : float Threshold~2500e float GND Float - GND

  • We took testbeam data with

floating Bias rail long time.

  • For the ASIC point of view, amplifier

should have low noise with bias rail to GND. (by Maurice.)

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SLIDE 34

Bias rail to GND v.s. floating

13th Dec 2019 Pixe 2018 34

2016Nov Target : th3000e Bias rail : GND Threshold~2300e 2016Aug Target : th3000e Bias rail : float Threshold~2500e float GND Float - GND

  • We took testbeam data with

floating Bias rail long time.

  • For the ASIC point of view, amplifier

should have low noise with bias rail to GND.

B

n+

Bias-rail Poly-Si P-stop Bump e- e- e- h h h

p Bulk

Al SiO2

  • V

Typical efficiency drop

Field to make efficiency drop by BR is milder in case BR floating?