Status of CLICdp pixel-detector readout systems Adrian Fiergolski - - PowerPoint PPT Presentation
Status of CLICdp pixel-detector readout systems Adrian Fiergolski Adrian.Fiergolski@cern.ch on behalf of the LCD vertex team CERN, EP-LCD 21 January 2016 Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21
Adrian Fiergolski Adrian.Fiergolski@cern.ch
CERN, EP-LCD
21 January 2016
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 1 / 16
1
Overview of the readout systems
2
Idea of the multi-chip DAQ chain
3
Timepix3-based telescope
4
Summary
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 2 / 16
ASIC Readout system Telescope Integration CLICpix + planar / CCPDv3 µASIC AIDA Mimosa telescope, Timepix3 telescope CLICpix2 + planar / C3PD µASIC 2.0 Timepix3 telescope Timepix FITPix AIDA Mimosa telescope Timepix3 CERN board/NIKHEF board + SPIDR AIDA Mimosa telescope, Timepix3 telescope Cracow SOI µASIC 2.0 (t.b.c.) Timepix3 telescope (t.b.c.) Investigator v1 (Alice) ? t.b.c. t.b.c. [ Black: done, blue: planned ] µASIC FITPix SPIDR
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 3 / 16
FPGA board — Digilent Atlys
Xilinx Spartan-6 1 Gbps Ethernet high speed VHDCI connector
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 4 / 16
µASIC board
8 × general purpose power supplies
◮ Maximum current 0.5 A ◮ Voltage range 0 – 4 V (set resolution 1 mV) ◮ Monitoring resolution : 1 mV / 25 µA
4 × voltage output (0 — 4 V, 12 bit) 4 × current output (-100 µA — 100 µA, 12 bit) 4 × voltage input (0 — 4 V, 12 bit) High voltage input 12 × general CMOS signals (Input / Output). Two independent groups (8+4) with adjustable voltage level 0.9 – 3.6 V (determined by one general purpose power supply) 12 × differential pairs (Input / Output). I2C bus
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 4 / 16
Chipboard
PCIe×8 edge connector
◮ cost effective and robust solution for the R&D scenario with a single interface
board and many replaceable chipboards
integrated CCPDv3 board temperature sensor small memory with a unique ID
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 4 / 16
improvements with respect to the CLICpix design: CLICpix CLICpix2 Matrix size [pixels] 64 × 64 128 × 128 Active area [mm2] 1.6 × 1.6 3.2 × 3.2 ToT counter 4 bits 5 bits ToA counter 4 bits 8 bits better noise isolation readout protocol based
configuration over SPI protocol
Status
currently under verification sensors are coming
◮ planar sensors with matching footprint already produced ◮ matching active HV-CMOS sensor C3PD is being finalised
submission of the chips planned in the first half of this year
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 5 / 16
Interface board — a new µASIC
possibly VHDCI (FMC to VHDCI converter on the FPGA motherboard) PCIe×8 general purpose power supplies (voltage and current outputs) with monitoring capabilities covering CLICpix2 requirements: 1.0VVDDD , 1.2VVDDA, 1.2VVSSA CML , 2.5VVDD CMOS high voltage input 1× unidirectional SERDES link 8 × LVCMOS (2.5V, 1.2V) signals (I/O) 4 × CML differential pairs (I/O) clock and trigger/shutter input (RJ45 compatible with TLU) support of the C3PD sensor (slow control, readout of test pixels) I2C bus
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 6 / 16
FPGA board — VC707
Xilinx Virtex-7 2 HPC FMC connectors 10 Gbps data link soft-core Leon processor for slow control
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 7 / 16
interface board + chipboard
two flavours:
◮ integrated interface and chipboard developed at NIKHEF ◮ separated by VHDCI connector interface and chipboard developed at CERN
FMC connector 8 × 640 Mbps SERDES links power domains: 1.5VVDD, 1.5VVDDA, 1.5VVDDPLL FEASTMP pluggable radiation and magnetic field tolerant 10 W DC/DC converter module
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 7 / 16
Features:
CLICpix2/Timepix3/FEI4/MuPix/... support
◮ set of simple PCIe chipboards provided by users
Zynq firmware and the interface board developed by collective effort
◮ collaboration with CaRIBOu project (Brookhaven National Lab,
University of Geneva, CERN)
FPGA and memory can be placed in a safe distance (∼50 cm) from the sensor assembly, to prevent radiation damage from sources or particle beams and facilitate mounting voltage regulators are close to the chip
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 8 / 16
Advantages: SoC (Z-7045) FMC HPC connector (8 GTX transceivers) FMC LPC connector (1 GTX transceiver) SFP+ connector availability cost effective and rapid solution for a small volume
Usage:
The integrated dual core ARM Cortex-A9 processor will run Linux OS providing Slow Control service via the Gigabit Ethernet interface. Data readout through 10 Gbps Ethernet (SFP+).
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 9 / 16
✞ ✝ ☎ ✆
✄ ✂
FMC mezzanine
◮ 400 pins vs legacy 68-pin VHDCI
✄ ✂
PCIe×16 receptacle for the chipboard
◮ 164 pins vs legacy 98-pin or 80-pin SEAM connector ◮ ×8 compatible with ×16 ◮ simple adapters, ex. PCIe edge to VHDCI (CERN Timepix3)
8 × general purpose power supplies with monitoring capabilities
◮ Maximum current: 4 A ◮ Voltage range 0 — 4 V
8 × voltage output (0 — 4 V) 4 × current output (0 — 100 µA) 4 × voltage input (0 — 4 V) FEASTMP support high voltage input
✄ ✂
8× full-duplex SERDES links ADC (8 channels, 80 MSPS/12-bit) 16 × general CMOS signals (I/O) with adjustable voltage levels differential pairs (I/O) — CML converters only on the specific chipboards clock and trigger/shutter input (RJ45 compatible with TLU) I2C bus
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 10 / 16
With help from the LHCb Velo upgrade group, a Timepix3 telescope setup has been built and is permanently installed at the end of the SPS-H6 beamline. SPIDR readout boards from NIKHEF, mounted outside a light-tight enclosure 6-8 telescope planes,
◮ with 300 µm thick p-in-n sensors rotated ◮ tilted by 9◦ in order to enhance charge sharing
trigger for non self-triggered DUTs
◮ 3 × scintillators + PMTs (HAMAMATSU H10721)
2 axes + rotation stage (Newport GTS70, GTS30V, URS50BCC, ESP301-3N) Rack-mounted readout server
◮ 16 cores, 32 GB RAM, 24 TB RAID-6 disk array, ◮ 8 × 10 Gbps Ethernet (10 Gbps link to EOS, Castor) Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 11 / 16
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 12 / 16
timing resolution: ≈ 1 ns spatial resolution: ≈ 2 µm particle rate: ≈ 1.5 × 106/spill (depends on beam configuration)
◮ maximum rate ≈ 10M tracks / spill
(Timepix3 limitation)
t_hit - t_track / s
5 10
10 × 100 200 300
3
10 ×
= 2.3ns σ Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 13 / 16
CLIC-specific extension has been added to the LHCb readout software: parameter scans: threshold, bias, translation/rotation support of the telescope-specific infrastructure:
◮ HV Keithley power supplies Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 14 / 16
CLIC-specific extension has been added to the LHCb readout software: parameter scans: threshold, bias, translation/rotation support of the telescope-specific infrastructure:
◮ HV Keithley power supplies
Set of Python scripts developed by the Timepix3 designers (Xavier Llopart) alternative way to perform chip equalization and calibration Future work: integration of the telescope with the EUDAQ 2.0 software
◮ producer implements FSM and follows commands distributed by run control
◮ data stored directly by the producer
consolidation of the Timepix3 DAQ source code (C++ and Python library)
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 14 / 16
CLICpix readout through µASIC platform flexible readout system (CLICpix2 and other readout chips)
◮ new version of the interface board (µASIC 2.0) ◮ system on chip (SoC) platform (CPU + FPGA in a single Zynq device) ◮ possibility of collaboration with CaRIBOu group
Timepix3-based telescope
◮ successfully commissioned in SPS H6 beamline ◮ at the moment operated by the extended LHCb framework ◮ eventually to be integrated with the EUDAQ software (AIDA-2020) Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 15 / 16
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 16 / 16
ASIC manufactured in 65 nm process node 25 µm × 25 µm pixels matrix of 64 × 64 pixels 1.6 × 1.6 mm2 active area Frame based acquisition (suits bunch structure of CLIC) Simultaneous ToT and ToA measurement
CCPDv 3 CLICp ix
Cfb
Vthr
Feedback network
T
logic T
logic 4-bit TOT counter 4-bit TOA/Event counter Compresion logic previous pixel next pixel
CLICpix
CLICpix standalone and with sensors (”active” HV-CMOS, planar silicon) testing showed full functionality of the chip.
Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 18 / 16