Speeding Up Quantifjed Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions
Martin Jonáš, Jan Strejček
Fondazione Bruno Kessler, Italy Faculty of Informatics, Masaryk University, Czech Republic
Speeding Up Quantifjed Bit-Vector SMT Solvers by Bit-Width - - PowerPoint PPT Presentation
Speeding Up Quantifjed Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions Martin Jon , Jan Strejek Fondazione Bruno Kessler, Italy Faculty of Informatics, Masaryk University, Czech Republic In many software verifjcation
Fondazione Bruno Kessler, Italy Faculty of Informatics, Masaryk University, Czech Republic
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1 How to decide satisfjability using bit-width reductions 2 How to decide unsatisfjability using bit-width reductions 3 Our implementation in a single algorithm 4 Experimental evaluation
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1 Reduce the formula. 2 Try to solve its satisfjability. 3 Get a symbolic model/countermodel. 4 Extend the symbolic model/countermodel to the original bit-width. 5 Check whether it is a symbolic model/countermodel of the original formula. 6 If unsuccessful, increase the reduction bit-width and repeat.
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0.01 0.1 1 10 100 T/O 0.01 0.1 1 10 100 T/O
2017−Preiner−keymaera 2017−Preiner−psyco 2017−Preiner−scholl−smt08 2017−Preiner−tptp 2017−Preiner−ua 20170501−Heizmann−ua 2018−Preiner−cav18 wintersteiger
sat TIMEOUT (timeout) unsat
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0.01 0.1 1 10 100 T/O 0.01 0.1 1 10 100 T/O
2017−Preiner−keymaera 2017−Preiner−psyco 2017−Preiner−scholl−smt08 2017−Preiner−tptp 2017−Preiner−ua 20170501−Heizmann−ua 2018−Preiner−cav18 wintersteiger
sat TIMEOUT (timeout) unsat
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0.01 0.1 1 10 100 T/O 0.01 0.1 1 10 100 T/O
btor|cvc4 time (s) btor|cvc4−r time (s)
0.01 0.1 1 10 100 T/O 0.01 0.1 1 10 100 T/O
btor|q3b time (s) btor|q3b−r time (s) Family
2017−Preiner−keymaera 2017−Preiner−psyco 2017−Preiner−scholl−smt08 2017−Preiner−tptp 2017−Preiner−ua 20170501−Heizmann−ua 2018−Preiner−cav18 wintersteiger
Result
sat TIMEOUT (timeout) unsat
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