Solving the Discrete Logarithm of a 113-bit Koblitz Curve with an - - PowerPoint PPT Presentation

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Solving the Discrete Logarithm of a 113-bit Koblitz Curve with an - - PowerPoint PPT Presentation

Solving the Discrete Logarithm of a 113-bit Koblitz Curve with an FPGA Cluster Erich Wenger and Paul Wolfger Graz University of Technology WECC 2014, Chennai, India We solved the discrete logarithm of a 113-bit Koblitz Curve.


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Solving the Discrete Logarithm of a 113-bit Koblitz Curve with an FPGA Cluster

Erich Wenger and Paul Wolfger Graz University of Technology WECC 2014, Chennai, India

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We solved…

  • the discrete logarithm of a 113-bit Koblitz Curve.
  • Challenge generated using SHA-256
  • Extrapolated 24 days on 18 Virtex-6 FPGAs
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ECDLP Records

  • In 2000: 


Binary Koblitz curve - ECC2K-108 
 using 9,500 PCs in 126 days

  • In 2004: 


Binary elliptic curve - ECC2-109 
 using 2,600 PCs for 510 days

  • In 2012: 


Elliptic curve over 112-bit prime field 
 using 200 Playstation 3 for 6 months

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TU Graz Records

  • IT-Security Lecture
  • 2012: 75 bit in days on quad-core
  • 2013: 80 bit in 17 days on Core i5-2400
  • Master project:
  • Virtex 6 FPGA
  • 83 bit in (avg) 4.1 days
  • Room for improvement…
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The higher the security level… …the lower the speed. With knowledge on the best attacks… …realistic security bounds are possible. …potentially smaller parameters can be used. …potentially faster algorithms can be used.

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Elliptic Curve 
 Discrete Logarithm Problem

Parallelized Pollard’s Rho Algorithm

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We are looking for…

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Pollard’s Rho Algorithm

Iteration function Parallelized Pollard’s Rho

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Iteration Function

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Reference Iteration function Expected Measured iterations iterations Teske [29] f(Xi) = Xi + R[j] 929 · 103 906 · 103 Wiener and Zuccherato [31] f(Xi) = min

0≤l<m

  • σl(Xi + R[j])

145 · 103 147 · 103 Gallant et al. [14] f(Xi) = Xi + σl(Xi) 145 · 103 166 · 103 Bailey et al. [4] f(Xi) = Xi + σ(l mod 16)/2+3(Xi) 145 · 103 166 · 103

Iteration Function

41-bit Koblitz Curve

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Architecture

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FPGA Development Board

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One NAND Gate:

  • 4 Transistors
  • 3.136 @ UMC 90nm
  • Register/Flip-flop:


~5 GE

ASIC Design

AND OR NAND NOR XNOR XOR

µm2 1 GE 1.25 1.25 2.5 2.5 1

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FPGA Design

X-Ref Target - Figure 3 A6:A1 D COUT D DX C CX B BX A AX O6 DI2 O5 DI1 MC31 WEN CK DI1 MC31 WEN CK DI1 MC31 WEN CK DI1 MC31 WEN CK ug364_03_040209 DX DMUX D DQ C CQ CMUX B BQ BMUX A AQ AMUX Reset Type D FF/LAT INIT1 INIT0 SRHI SRLO SR CE CK FF/LAT INIT1 INIT0 SRHI SRLO FF/LAT INIT1 INIT0 SRHI SRLO FF/LAT INIT1 INIT0 SRHI SRLO D SR CE CK D SR CE CK D SR Q CE CK CIN 0/1 WEN CK Sync/Async FF/LAT A6:A1 O6 O5 C6:1 CX D6:1 DI A6:A1 O6 O5 B6:1 BX A6:A1 W6:W1 W6:W1 W6:W1 W6:W1 O6 O5 A6:1 AX SR CE CLK CE Q CK SR Q Q Q SRHI SRLO INIT1 INIT0 D CE Q CK SR SRHI SRLO INIT1 INIT0 D CE Q CK SR SRHI SRLO INIT1 INIT0 D CE Q CK SR SRHI SRLO INIT1 INIT0 DI2 DI2 DI2 CI BI AI

LUT FF

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FPGA Development Board

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Multiple Small Cores

Time Area

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Core Idea

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ECC Breaker NextInput Iteration Function Point Addition Point Automorphism FIFO adder multiplier FIFO FIFO Xi ci di Xi+1 ci+1 di+1 Branching Table multiplier squarer inverter adder multiplier Interface Distinguished Point Storage Lambda Table F2m F2m F2m

Fn Fn Fn Fn

79 %

14 %

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Point Addition and 
 FF Inversion

S + M 3S + M 7S + M 14S + M 28S + M 56S + M S + M S + M S

y1 y2 x1 x2 ADD ADD FIFO FIFO ADD a FIFO FIFO INV MUL SQU MUL ADD ADD FIFO ADD x3 y3

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Binary Field Multiplier

Method Size Parallel 5,497 LUTs Mastrovito 7,104 LUTs Bernstein’s Batch Binary Edwards 4,409 LUTs Recursive Karatsuba 3,757 LUTs

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Point Automorphism

Square Square Compare x y x' y' x y x' y'

smallest Point

σi(P)

i+1

σi+1(P)

comparator tree x y rot 0 rot 1 rot 2 rot 3 C → N C → N FIFO BARREL ROTATE N → C N → C FIFO x' y' ...

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Details

  • 210 pipeline stages
  • Per default: canonical basis
  • Normal basis used for point automorphism module
  • Karatsuba Multiplier for
  • Itoh-Tsujii Inversion
  • Montgomery Multiplier based on DSP slices

Fn

F2m tion m F2m tion m

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Computation Time

Distinguished Triples 1,750,000 3,500,000 5,250,000 7,000,000 Time [Days] 10 20 30 40 50

April 19th, 2014 Extrapolated: 24 days

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Challenge Generation

import hashlib PX = str_to_poly(hashlib.sha256(str (0)). hexdigest ()) PY= PolynomialRing (K, ’PY’).gen() P_ROOTS = (PY^2+PX*PY+PX^3+a*PX^2+b). roots () P=E([PX ,P_ROOTS [0][0]]); P=P*h QX = str_to_poly(hashlib.sha256(str (1)). hexdigest ()) Q_ROOTS = (PY^2+QX*PY+QX^3+a*QX^2+b). roots () Q=E([QX ,Q_ROOTS [0][0]]); Q=Q*h

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Different FPGAs

Series Development Kit LUTs used maximum Frequency Price Virtex-6 ML605 38% 261 MHz 2,495 USD Spartan-6 LX150T

  • 147 MHz

995 USD Artix-7 AC701 62% 264 MHz 999 USD Virtex-7 VC707 28% 313 MHz 3,495 USD Kintex-7 KC705 42% 313 MHz 1,695 USD

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Different Targets

Target Iterations Costs [USD] Days (Estimated) ECC2K-112 8.5 x 10 42,000 22 ECC2-113 90 x 10 42,000 118 ECC2K-130 4,055 x 10 1,000,000 127 ECC2-131 46,239 x 10 10,000,000 145 ECC2-163 3,030 x 10 1,000,000,000 189,934

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Open Issues

  • Power problems
  • Maximum frequency: 165 MHz vs 275 MHz
  • Multiple instances
  • Negation map and fruitless cycles
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Random Facts

  • Necessary budget:
  • 18 FPGAs: 2,500 USD x 18 = 45,000 USD
  • Power consumption: different budget :-)
  • 1.5 man-years: 100,000 USD (different budget)
  • Money actually spent: 20 EUR on chocolate
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Room for improvement

YES!!!

2x speed equals 2 extra bits to attack 128x speed equals 14 extra bits to attack

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0" 10" 20" 30" 40" 50" 60" 70" 1 1 3 * b i t " K

  • b

l i t z " a = 1 " 1 1 3 * b i t " K

  • b

l i t z " a = " 1 1 3 * b i t " W e i e r s t r a s s " 1 2 7 * b i t " K

  • b

l i t z " a = 1 " 1 2 7 * b i t " K

  • b

l i t z " a = " 1 2 7 * b i t " W e i e r s t r a s s " 1 3 1 * b i t " K

  • b

l i t z " a = 1 " 1 3 1 * b i t " K

  • b

l i t z " a = " 1 3 1 * b i t " W e i e r s t r a s s " Expected(Number(of(Itera2ons([bits]( Without"Speedup" With"Speedup"

New Challenges

Prime numbers: 109, 113, 127, 131, …

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New Challenges

Prime numbers: 109, 113, 127, 131, …

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Solving the Discrete Logarithm of a 113-bit Koblitz Curve with an FPGA Cluster

Erich Wenger and Paul Wolfger Graz University of Technology WECC 2014, Chennai, India