SOFTWARE IMPLEMENTATION OF THE IEEE 802 11A/P PHYSICAL LAYER IEEE - PowerPoint PPT Presentation

SOFTWARE IMPLEMENTATION OF THE IEEE 802 11A/P PHYSICAL LAYER IEEE 802.11A/P PHYSICAL LAYER SDR`12 – WInnComm Europe SDR 12 WInnComm Europe 27  29 June, 2012  Brussels, Belgium T. Cupaiuolo, D. Lo Iacono, M. Siti and M. Odoni Advanced System Technologies STMicroelectronics, Agrate Brianza, Italy Daniele Lo Iacono i l

Outline  The system  Wireless Access in Vehicular Environments (WAVE): IEEE 802.11p Wireless Access in Vehicular Environments (WAVE): IEEE 802 11p  Comparison with IEEE 802.11a/g  A Software Defined Radio (SDR) implementation approach: the BPE A Software Defined Radio (SDR) implementation approach: the BPE baseband communication platform  Digital baseband implementation  Reference system model  802.11p: Data-aided channel estimation  Customization and code profiling Customization and code profiling  Results 2

IEEE 802.11p WAVE  Requirements  Fast access as a priority (latency <50 ms) p y ( y )  Mobility (>60Km/h) and Range (~1Km)  Robustness and reliability  Security  Applications  Vehicle safety (emergency warning systems, Intersection collision avoidance, forward collision warning) g)  Tolling  Infotainment  Traffic management g  Cooperative Adaptive Cruise Control  Comparison with 802.11a/g  10 MHz OFDM bandwidth (vs 20 MHz): max PHY data rate 27 Mbit/s (vs 54) 10 MHz OFDM bandwidth (vs 20 MHz): max PHY data rate 27 Mbit/s (vs. 54)  5.9 GHz carrier frequency  digital baseband: added support for mobility → Data-aided channel estimation 3

The BPE baseband communication platform reconfigurable data-path distributed customizable customizable embedded coarse-grain memory hardware mesh operators d ‐ memory d memory d ‐ unit d ‐ unit routing bank bank instruction memory d ‐ instruction memory scheduler scheduler and management dispatcher dispatcher fetch & registers space b ‐ instruction decoding execution data ‐ port data port system bus interface 4

Flow-control: b-instruction out = opcode(in0,in1,in2) mesh d ‐ memory y d ‐ unit d ‐ unit routing bank bank instruction memory b-instruction are also used are also used to set the way d ‐ instruction memory d-instruction scheduler management will access the b-instruction memory bank memory bank fetch execution unit & registers space b ‐ instruction decoding execution data ‐ port data port system bus interface register file 5

Vector processing: d-instruction out = unit1.opcode(unit0,in0,in1) bank of static processing units memories for performing mesh vector allocation parallel and d ‐ memory d memory d ‐ unit d ‐ unit pipelined vector routing bank bank instruction processing memory routing mesh routing mesh dynamically configuring d ‐ instruction memory scheduler unit-memory management and unit-unit a d u t u t d instruction d-instruction fetch connections scheduling unit & registers space b ‐ instruction decoding execution data port data ‐ port system bus interface 6

Algorithm mapping: macros v0 v7 arith0.mul comm0.ed v8 v1 v3 v9 macro made by arith1.mul arith2.sub comm1.qt arith3.mul two parallel ll l t branches each v2 v4 v5 v6 performing pipelined processing among i parallel and different units pipelined processing arith0.mul to reduce execution time and memory y comm0.ed comm0 ed v9 = arith3.mul(comm1,v6) 9 ith3 l( 1 6) accesses comm1.qt(arith2,v5) v8 = arith2.sub(v4,arith1) arith1.mul v7 = comm0.ed(arith0,v3) arith0.mul(v0,v1); arith2.sub i h2 b arith1.mul(v0,v2) comm1.qt arith3.mul 7

Pipeline of macros v0 v2 v3 v1 macro #0 macro #1 macro #2 macro #0 macro #0 macro #1 macro #1 macro #2 macro #2 conflicts on shared memory access memory access use of memory alias f li inhibit a full pipelined (ping-pong mechanism) processing at intermediate stage of processing v0 r0 r1 v1 macro #0 macro #1 macro #2 macro #0 macro #0 macro #0 macro #1 macro #1 macro #1 macro #2 macro #2 macro #2 8

Multi-thread macro #0 macro #0 macro #0 macro #1 macro #1 macro #1 macro #1 macro #1 macro #1 macro #2 macro #2 macro #2 function Single ‐ thread execution OFDM symbol #1 OFDM symbol #2 function #1 function #2 function #3 function #1 function #2 function #3 Multi ‐ thread (3) execution OFDM #4 function #1 function #1 OFDM #1 OFDM #2 OFDM #3 OFDM #3 OFDM #4 function #2 function #2 OFDM #1 OFDM #2 OFDM #1 OFDM #2 OFDM #3 OFDM #4 function #3 function #3 9

IEEE 802.11a/p reference system model source puncturer+ upsampling/ encoder mapper IFFT D/A bits interleaver filtering channel de ‐ int Viterbi decoded A/D / filter FFT equalizer q de ‐ map p d de ‐ punct t decoding d di b bits discard pilot and virtual sub ‐ carriers channel synchronizer synchronizer estimation 802.11p: data -aided channel estimation channel estimation 10

Data-aided channel estimation (1/2)  Data-aided channel estimation basic idea: 1 1. data detection of the current received OFDM symbol using channel d t d t ti f th t i d OFDM b l i h l estimation corresponding to the previous OFDM symbol 2. the channel corresponding to the current OFDM symbol is estimated p g y by using the estimated data QAM symbols  Data detection through simple hard decision detection (HDD)  low extra complexity  l low latency compared to 802.11a/g l t d t 802 11 / 11

Data-aided channel estimation (2/2) Initial CE based on the LTS field LTS based Time Domain initial CE received freq. domain CE Least Square CE sequence (FFT) time ‐ domain IFFT FFT filtering For successive OFDM symbols (SIG and DATA) CE tracked exploiting both pilot and the estimated data symbols and the estimated data symbols previous CE previous CE Data ‐ aided Data ‐ aided Time Domain Time Domain HDD updated CE freq. domain CE Least Square CE received sequence (FFT)

Multimode 11a/p receiver data pipeline de ‐ int Viterbi filter FFT equalizer de ‐ map de ‐ punct decoding channel recursive update : processing synchronizer estimation estimation bottleneck which does not allow bottleneck which does not allow to build a pipeline as for 802.11a 11a N N N 1 N+1 N ‐ 1 N N ‐ 2 N ‐ 1 symbol processing time 11p N N N N+1 N+1 N+1 N N+1 symbol processing time 13

Multimode 11a/p receiver code profiling de ‐ int Viterbi filter FFT equalizer de ‐ map de ‐ punct decoding channel synchronizer estimation function 11a/g (clock cycles) 11p (clock cycles) filter 162 synchronizer h i 1536 (l t 1536 (latency) ) FFT (iFFT) 200 (radix-4) channel estimation 64 (@LTS) 759 (data-aided, hard-detection) equalizer 64 de-mapper 348 (MCS #7) de-interleaver / de-puncturer 408 (MCS #7) OFDM symbol single-thread 1432 ( 5.7  s ) 2150 ( 8.6  s ) (@250MHz) OFDM symbol multi-thread 596 ( 2.4  s )  ) 1490 ( 5.9  s )  ) ( ( (@250MH ) (@250MHz) 14

Conclusions  The BPE software programmable architecture has support for:  macro building  (macro-) instructions pipelining  emulate memory ping-pong access  Multi-threading  Algorithm profiling on the BPE Al ith fili th BPE  Translate the algorithm steps into macros  Build the macro-pipeline  PHY profiling on the BPE (MCS #7, @250 MHz) 802.11a/g: 5.7  s (single thread)  2.4  s (three threads) (i.e. 54 Mbit/s)  802 11p: 8 6  s (single thread) 802.11p: 8.6  s (single thread)  5.9  s (two threads) (i.e. 27 Mbit/s) 5 9  s (two threads) (i e 27 Mbit/s)    Future steps   802 11p 20 MHz optional mode 802.11p 20 MHz optional mode  Soft decision directed DA CE (FEC based, i.e. Viterbi decoding)  to address these and other issues: investigating architectural enhancements (including the idea of a “cluster of BPE”) ( g ) 15