Soft Decision Based Triple-Concatenated FEC for 100 Gb/s Submarine - - PowerPoint PPT Presentation

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Soft Decision Based Triple-Concatenated FEC for 100 Gb/s Submarine Cable Systems

• K. Onohara, K. Kubo, Y. Miyata,
• H. Yoshida, and T. Mizuochi

Mitsubishi Electric Corporation

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Presenter Profile

Kiyoshi Onohara received the B.E., M.E., and Ph.D. degrees in communication engineering from Osaka University, Osaka, Japan, in 2000, 2002, and 2005, respectively. In 2005, he joined Mitsubishi Electric Corporation,

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In 2005, he joined Mitsubishi Electric Corporation, Kamakura, Kanagawa, Japan, where he has been engaged in research and development of the applications of forward error correction, optical cross-connect, and supervisory system for

• ptical transport networks.

Kiyoshi Onohara Researcher Email: Onohara.Kiyoshi@eb.MitsubishiElectric.co.jp Tel: (+81) 467 41 2443

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Outline

Introduction

Motivation for Developing Strong FEC for 100 Gb/s Systems

Soft Decision FEC in Digital Coherent Transceivers Triple-Concatenated FEC

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Triple-Concatenated FEC

Algorithm of the proposed FEC Simulation result

Impact on the Next Gen. Submarine Cable Systems Conclusion

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Needs Higher SNR for 100Gb/s Systems

In the pursuit of high speed transmission, we should consider that multi-level modulation needs a higher SNR than binary formats. This has increasingly motivated research activity of more powerful, but nevertheless practical FEC for the improvement of OSNR tolerance in 100G digital coherent systems.

PSK 18 m) 4 64-QAM 16-QAM 8-PSK QPSK 2 4 6 8 10 12 14 16 10 100

DPSK OOK DQPSK OOK DP-16QAM DQPSK DPSK DP-QPSK DP-16QAM DP-QPSK

20 40 Bit rate (Gb/s) Required OSNR (dB in 0.1nm)

5.7dB 1.3dB 2.7dB

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Soft Decision FEC in Digital Coherent (1)

Conveniently, a digital coherent receiver incorporates A/D converters (ADCs) at its front-end for demodulating multi-level coded signals This suddenly makes it much easier to realize soft-decision decoding

DP-QPSK

6-bit ADC Euclidean

6-bit 6-bit 3-bit

100G DP-QPSK Digital Coherent LSI 5

DP-QPSK RX Module

6-bit ADC 6-bit ADC 6-bit ADC DSP (CR, FDE

• Pol. Demux)

Euclidean Distance LLR Calc. Soft Dec. FEC Decoder r

(00) (01) (11) (10)

Corrected Output DP-QPSK Euclidean Distance

DSP: Digital Signal Processor, CR: Carrier Recovery, FDE: Frequency Domain Equalizer, LLR: Log-likelihood Ratio

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Soft Decision FEC in Digital Coherent (2)

Digital Signal Processor

• OIF proposed that the low-redundancy hard decision FEC on OTU4 framer as the outer

codes.

• The inner FEC encoder/decoder is implemented into transceiver module as an option.
• The concatenation with 7% EFEC and soft decision FEC is good solution.
• This architecture facilitates the implementation issues underlying not only transceiver

module but also 100G framer.

6 Client ENC DEC OTU4 Framing OTU4 Framer and EFEC OTU4 De- framing

O/E E/O

Digital Coherent RX /DEMUX

DSP / MUX Optical Channel Hard-decision EFEC (outer code) Client ENC DEC Code A Code B

Iteration

Soft-decision LDPC (inner code) I/O I/O I/O I/O Digital Signal Processor with Soft-decision LDPC DEC Code C ENC

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Triple-Concatenated FEC

• LDPC is one of the potential candidates for strong soft decision FEC in 100Gb/s systems.
• The redundancy of the LDPC(9216,7936) developed in 2009, is 16%.
• The ratio of the LDPC(4608,4080) code of the proposed triple-concatenated FEC with

Enhanced FEC is 13%.

• By applying the shorter code length of LDPC, we suffer from the error floor performance.

Therefore LDPC concentrates the water fall region, and we use Enhanced FEC as the outer

• code. This does not degrade, but assists the coding gain.

Conventional FEC and frame format 16% 4%

LDPC: Low-Density Parity Check

7 Pre-FEC BER Post-FEC BER Pre-FEC BER Post-FEC BER Proposed FEC and frame format ~10-5 ~10-3 Inner FEC decoding Outer FEC decoding Payload LDPC

row1 row2 row3 row4

OH 13% 7% RS Payload LDPC

row1 row2 row3 row4

OH OTU4 frame EFEC

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Algorithms for LDPC

• od

variable offset BP

cyclic approx. d-min

• od

variable offset BP

cyclic approx. d-min

Conventional algorithms for LDPC codes Shuffled belief propagation (BP) algorithm – High-performance, but quite complex Offset BP-based algorithm – Approximation of shuffled BP – Performance is not so good

8 Comparison of decoding algorithms Performance Goo Bad Complexity Large Small min-sum shuffled BP

upgrade NCG easy calculation

• ffset BP

Performance Goo Bad Complexity Large Small min-sum shuffled BP

upgrade NCG easy calculation

• ffset BP

NCG : Net Coding Gain

We propose new algorithm; Variable offset BP-based algorithm – Designed to minimize the circuit complexity without degrading error correction performance. – This algorithm originated from the

• ffset BP-based algorithm.

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Comparison of Algorithms

• Error Correction Performance

– Performance evaluation by Monte Carlo simulations – Variable offset BP-based algorithm is better than the offset BP-based algorithm, the difference being about 0.1 dB.

1E-01 1E+00 Uncoded Variable offset BP-based Offset BP-based Cyclic approx. delta min Shuffled BP 1E-01 1E+00 Uncoded Variable offset BP-based Offset BP-based Cyclic approx. delta min Shuffled BP 9 Simulation results Simulation conditions Parameters of inner code LDPC (4608, 4080) Redundancy 12.94% Bit width of LLR (Input of decoder) 3 Noise model AWGN

LLR : Log-Likelihood Ratio

1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02 5.5 6.0 6.5 7.0 7.5 Q [dB] Bit Error Ratio Shuffled BP 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02 5.5 6.0 6.5 7.0 7.5 Q [dB] Bit Error Ratio Shuffled BP

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Performance Evaluation

• Performance evaluation by Monte Carlo simulations

– LDPC+EFEC has no error floor at least down to a post-FEC BER of 1E-11 – We expect that proposed concatenated codes can achieve a Q-limit of 6.4 dB (NCG of 10.8dB) at a post-FEC BER of 1E-15.

• 4.6 dB better than the standard RS(255,239) code

1E-01 1E-01 1E-01

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1E-15 1E-13 1E-11 1E-09 1E-07 1E-05 1E-03 5.5 6.0 6.5 7.0 7.5 Q [dB] Bit Error Ratio Uncoded LDPC only LDPC + EFEC 1E-15 1E-13 1E-11 1E-09 1E-07 1E-05 1E-03 5.5 6.0 6.5 7.0 7.5 Q [dB] Bit Error Ratio Uncoded LDPC only LDPC + EFEC 1E-15 1E-13 1E-11 1E-09 1E-07 1E-05 1E-03 5.5 6.0 6.5 7.0 7.5 Q [dB] Bit Error Ratio Uncoded LDPC only LDPC + EFEC

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Impact on Next Gen. Submarine Cable Systems

A digital coherent transceiver with this powerful FEC pushes a submarine line terminal equipment (SLTE) with 100 Gb/s interfaces towards fruition. A range of interfaces: 2 x 40 Gb/s and 10 x 10 Gb/s Relief from the need for dispersion compensation fibers by implementing a dispersion compensator in the DSP

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dispersion compensator in the DSP Pure-silica fiber can be installed when constructing new cable systems, resulting in reduced capital expenditure The powerful FEC enables us to migrate from existing 40 Gb/s long-haul systems to 100 Gb/s DP-QPSK systems

40G DPSK with EFEC 100G DP-QPSK with SD-FEC

Upgrade Scenario for submarine cable systems

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Conclusion

• We have proposed the triple-concatenated FEC for 100 Gb/s submarine cable

system. New algorithms of LDPC codes for soft-decision FEC were proposed. We showed the performance of LDPC(4608, 4080)+EFEC by Monte Carlo

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We showed the performance of LDPC(4608, 4080)+EFEC by Monte Carlo

• simulation. Expected to achieve a Q-limit of 6.4dB (NCG of 10.8dB) at a post-

FEC BER of 1E-15. It is anticipated that the proposed FEC scheme will be implemented in 100 Gb/s coherent DSP LSI in the near future.

This work was in part supported by the project of “Digital Coherent Optical Transceiver Technologies” of the Ministry of Internal Affairs and Communications (MIC) of Japan

2010

enabling the next generation of networks & services

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Pacifico Convention Plaza Yokohama & InterContinental The Grand Yokohama 11 ~ 14 May 2010 www.suboptic.org The 7th International Conference & Convention

• n Undersea Telecommunications