Single Electron Devices for Single Electron Devices for Logic - - PowerPoint PPT Presentation

Single Electron Devices for Single Electron Devices for Logic Applications Logic Applications

Reza M. Reza M. Rad Rad UMBC UMBC Based on pages 425 Based on pages 425-

• 441 of

441 of “ “Nanoelectronics Nanoelectronics and and Information Technology Information Technology” ”, Rainer , Rainer Waser Waser

Introduction Introduction

• Scaling down

Scaling down MOSFETs MOSFETs has been has been fundamental in improving the performance fundamental in improving the performance

• f ULSI circuits
• f ULSI circuits
• Scaling of

Scaling of MOSFETs MOSFETs is entering the deep is entering the deep sub 50 nm regime sub 50 nm regime

• Quantum mechanical effects are expected

Quantum mechanical effects are expected to be effective in these small structure to be effective in these small structure devices devices

Introduction Introduction

• A new device having operation principles

A new device having operation principles effective in smaller dimensions which effective in smaller dimensions which utilizes quantum utilizes quantum-

• mechanical effects

mechanical effects

• Single electron devices retain their

Single electron devices retain their scalability even on an atomic scale scalability even on an atomic scale

• Single electron devices will reduce the

Single electron devices will reduce the power consumption because the number power consumption because the number

• f electrons transferred from voltage
• f electrons transferred from voltage

source to ground is limited source to ground is limited

Single Single-

• electron box

electron box

• A quantum dot connected with two

A quantum dot connected with two electrodes electrodes

• One electrode connected to dot through a

One electrode connected to dot through a tunneling junction tunneling junction

• The other electrode, gate, coupled with

The other electrode, gate, coupled with quantum dot via insulator, electron cannot quantum dot via insulator, electron cannot pass through tunneling pass through tunneling

Single Single-

• electron box

electron box

• Electrons are injected/ejected to/from the dot

Electrons are injected/ejected to/from the dot through the tunneling junction (fig 1) through the tunneling junction (fig 1)

Single Single-

• electron box

electron box

• Basic operation of single

Basic operation of single-

• electron box:

electron box:

• As the size of quantum dot decreases, charging

As the size of quantum dot decreases, charging energy energy Wc Wc of a single excess charge on the dot

• f a single excess charge on the dot

increases increases

• If

If Wc Wc is sufficiently larger than thermal energy, is sufficiently larger than thermal energy, no electron tunnels to/from quantum dot no electron tunnels to/from quantum dot

• Electron number in the dot takes a fixed value

Electron number in the dot takes a fixed value

• The charging effect which controls

The charging effect which controls injection/ejection of a single charge to/from a injection/ejection of a single charge to/from a quantum dot is called quantum dot is called Coulomb Blockade Coulomb Blockade effect effect

Single Electron Devices Single Electron Devices

• Condition for Coulomb blockade:

Condition for Coulomb blockade:

• By applying a positive bias to the gate

By applying a positive bias to the gate electrode we could attract an electron to the electrode we could attract an electron to the quantum dot quantum dot

• Further increase of the gate voltage causes an

Further increase of the gate voltage causes an electron to enter the dot electron to enter the dot

• In single

In single-

• electron box, the electron number of

electron box, the electron number of the box is controlled, one by one, by utilizing the box is controlled, one by one, by utilizing the gate electrode the gate electrode

T k C e W

B c

>> = 2

2

Single Single-

• electron box

electron box

• Conditions for observing single

Conditions for observing single-

• electron

electron tunneling phenomena tunneling phenomena

• First: charging energy of a single electron to

First: charging energy of a single electron to the dot must be greater than thermal energy the dot must be greater than thermal energy

• Second: tunneling resistance

Second: tunneling resistance R Rt

t of the

• f the

tunneling junction must be larger than tunneling junction must be larger than resistance quantum h/e resistance quantum h/e2

2

• This is required to suppress the quantum

This is required to suppress the quantum fluctuations in electron number, n, of the dot fluctuations in electron number, n, of the dot

Single Single-

• electron box

electron box

• This condition is obtained as follows:

This condition is obtained as follows:

Ω ≈ >> > = ∆ ≈ ∆ ∆ > ∆ ∆ k 8 . 25 C R ). / ( : Then C R : charging the

• f

lifetime the be let / : dot quantum the

• f

energy charging the be let . : principle ty Uncertaini

2 2 t 2 t 2

e h R h R e C e t C e W W h t W

t t

Single Single-

• electron box

electron box

• Bias conditions for Coulomb Blockade Effects

Bias conditions for Coulomb Blockade Effects

• The voltage range which keeps electron number at n, is

The voltage range which keeps electron number at n, is extracted by considering the free energy of the system extracted by considering the free energy of the system

• F(n

F(n) free energy having n electrons in the island ) free energy having n electrons in the island

• Wc(n

Wc(n) : Charging energy ) : Charging energy

• A(n

A(n) : Work done by the voltage source connected to gate in order ) : Work done by the voltage source connected to gate in order to change the electron number from 0 to n to change the electron number from 0 to n

• Polarization charge in capacitors: due to rearrangement of elect

Polarization charge in capacitors: due to rearrangement of electrons rons

capacitors gate and junction tunneling

• n the

charge

• n

polarizati the are and ) ( ) ( ) (

g t g g g t t g t c

Q Q V C Q C Q ne Q Q n A n W n F = + − = − − =

Single Single-

• electron box

electron box

• Bias conditions ..

Bias conditions ..

g g g g g t g g g g g g t g g t g g t t c

C e n V C e n n F n F C V C C V C C en V Q dt V t I n A C C C C V C C C n e C Q C Q n W ] 2 1 [ ] 2 1 [ ) 1 ( ) ( : dot quantum in number electron maintain To ). ( ) ( , 2 1 2 2 2 ) (

2 2 2 2 2 2

+ < < − ⇒ ± < + = = = + = + = + =

Σ Σ Σ Σ Σ

∫

Single Single-

• electron box

electron box

• Bias conditions ..

Bias conditions ..

1

] 1 [ 2 : Where ) ( ) ( ) 1 ( ) 1 , ( : 1 n n to from number electron

• f

n transitio in the change energy Free

−

+ = − = − + = + ∆ +

t g c c t t

C C e Q Q Q C e n F n F n n F

Single Single-

• electron transistor

electron transistor

• Schematic structure of a

Schematic structure of a single single-

• electron transistor

electron transistor (SET) is shown in the (SET) is shown in the figure (fig 3) figure (fig 3)

Single Single-

• electron transistor

electron transistor

• Operation of a single

Operation of a single-

• electron transistor

electron transistor

• The circuit connected to the tunneling junction of source

The circuit connected to the tunneling junction of source is shown in the figure (fig4a) is shown in the figure (fig4a)

• The condition for maintaining electron number at n is:

The condition for maintaining electron number at n is:

] 2 [ 1 ] 2 [ 1 ] 2 1 [ ] 2 1 [

g g d d g g d d g d g d d g g d g

V C e ne C V V C e ne C C C e n C C V C V C C C e n − + < < − − ⇒ + + < + + < + −

Single Single-

• electron transistor

electron transistor

• The circuit connected to the tunneling junction

The circuit connected to the tunneling junction

• f drain is transformed to the circuit shown in
• f drain is transformed to the circuit shown in

the figure (fig 4b) the figure (fig 4b)

• The condition to maintain the electron number

The condition to maintain the electron number at n is at n is

] 2 [ 1 ] 2 [ 1

g g g s d g g g s

V C e ne C C V V C e ne C C + − − + > > + + − +

Single Single-

• electron transistor

electron transistor

• Figure (fig 5a) shows the drain

Figure (fig 5a) shows the drain-

• gate voltage

gate voltage relation relation

• Gray areas are coulomb blockade areas

Gray areas are coulomb blockade areas where electron number in the dot is fixed where electron number in the dot is fixed

Single Single-

• electron transistor

electron transistor

• Green areas are regions with two

Green areas are regions with two preferable electron numbers (one for preferable electron numbers (one for source and one for drain) source and one for drain)

• In area labeled A:

In area labeled A:

• Preferable electron number for source is 1

Preferable electron number for source is 1 and for drain is 0 and for drain is 0

• Electron tunnels from source to dot to make

Electron tunnels from source to dot to make its electron number 1 its electron number 1

• Then it tunnels from dot to drain to change

Then it tunnels from dot to drain to change the electron number of the dot to 0 the electron number of the dot to 0

Single Single-

• electron transistor

electron transistor

• Figure (fig 5b) shows the oscillating I

Figure (fig 5b) shows the oscillating Ids

ds versus

versus V Vg

g characteristic of the

characteristic of the SETs SETs

• Typical I

Typical Ids

ds versus

versus V Vds

ds characteristics are shown

characteristics are shown in figure (fig 5c) in figure (fig 5c)

Single Single-

• electron transistor

electron transistor

• Figure (fig 6)

Figure (fig 6) demonstrates a demonstrates a implementation of a implementation of a circular disk quantum circular disk quantum dot sandwiched between dot sandwiched between source and drain and source and drain and surrounding gate surrounding gate

Single Single-

• electron transistor

electron transistor

• Figure (fig 7) shows Ids

Figure (fig 7) shows Ids-

• Vg characteristics of

Vg characteristics of the fabricated SET, inset of the figure is the the fabricated SET, inset of the figure is the electron addition energies and part b shows electron addition energies and part b shows the energy required for adding electrons the energy required for adding electrons

Single Single-

• electron transistor

electron transistor

• Advantages and disadvantages of

Advantages and disadvantages of SETs SETs compared compared to to MOSFETs MOSFETs

• SETs

SETs: :

• low power consumption

low power consumption

• Good scalability

Good scalability

• Operation of

Operation of SETs SETs is limited to low temperatures is limited to low temperatures

• High output impedance (

High output impedance (Rt Rt must be much higher than must be much higher than 25.8 25.8 kOhms kOhms) )

• Source

Source-

• drain voltage of the

drain voltage of the SETs SETs must be smaller than must be smaller than the gate swing voltage the gate swing voltage

• For room temperature operation, dot must be much

For room temperature operation, dot must be much smaller than 10 nm, fabrication of a 10 nm structure is smaller than 10 nm, fabrication of a 10 nm structure is difficult in current technology difficult in current technology

Other Single Electron Devices Other Single Electron Devices

• Other single electron devices

Other single electron devices

• Single electron turnstile and single electron

Single electron turnstile and single electron pump are devices that can control timing of pump are devices that can control timing of single electron tunneling single electron tunneling

• Fabrication of single electron devices

Fabrication of single electron devices

• Single electron devices have been fabricated

Single electron devices have been fabricated in a variety of materials such as aluminum, in a variety of materials such as aluminum, hetrostructures hetrostructures and silicon and silicon

• Fabrication on silicon is done by fine

Fabrication on silicon is done by fine-

• lithography or by growth of silicon dots by

lithography or by growth of silicon dots by deposition process deposition process

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• Introduction

Introduction

• Many attempts have been made to develop logic

Many attempts have been made to develop logic circuits consisting of single electron devices circuits consisting of single electron devices

• Two approaches in logic applications:

Two approaches in logic applications:

• Representing a bit by a single electron and using single

Representing a bit by a single electron and using single electron devices to transfer electrons one by one electron devices to transfer electrons one by one

• Representing a bit by more than a single electron and

Representing a bit by more than a single electron and using single electron devices to switch the current using single electron devices to switch the current

• n/off
• n/off
• Former uses less power, latter results in more

Former uses less power, latter results in more

• peration stability
• peration stability

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• Analytical model of SET for circuit simulation

Analytical model of SET for circuit simulation

• Assumptions

Assumptions

• Source and drain of the

Source and drain of the SETs SETs are connected to are connected to capacitors much larger than total capacitance of the capacitors much larger than total capacitance of the SET island or biased by constant voltage sources SET island or biased by constant voltage sources

• Source and drain resistances are assumed to be the

Source and drain resistances are assumed to be the same ( same (Rs Rs=Rd= =Rd=Rt Rt) )

• At each given gate voltage, the two most probable

At each given gate voltage, the two most probable numbers of electrons in the SET island are taken into numbers of electrons in the SET island are taken into account account

• Tunneling resistance is supposed to be much larger

Tunneling resistance is supposed to be much larger than quantum of resistance h/e than quantum of resistance h/e2

2~25.8kOhms

~25.8kOhms

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• Derivation of the model

Derivation of the model

• I

I-

• V characteristics of SET having n or n+1 electrons is given by

V characteristics of SET having n or n+1 electrons is given by

) ( , 2 ~ , ~ , 2 1 ). ( 2 ~ ) ~ / ~ sinh( ~ ) ~ / ~ sinh( ) ~ / ~ sinh( ) ~ ~ ( 2

2 , , 2 2 , d s t t t B ds ds ds d s g g g n gs ds ds gs n gs ds ds n gs n

R R R R R R e TC k T e V C V n e V C C C e V C V where T V V T V V T V V V C R e I = = + = = = − − − + − = − − =

Σ Σ Σ Σ Σ

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• It corresponds to one period of Coulomb oscillations

It corresponds to one period of Coulomb oscillations

• Gate voltage giving peak of Coulomb oscillations is:

Gate voltage giving peak of Coulomb oscillations is:

• Considering the period of Coulomb oscillations e/Cg,

Considering the period of Coulomb oscillations e/Cg, gate voltage range is obtained as gate voltage range is obtained as

g ds d s g g g gs

C V C C C C ne C e V 2 ). ( 2 − + + + =

g ds d s g g gs g ds d s g g

C V C C C C e n V C V C C C C ne 2 ). ( ) 1 ( 2 ). ( − + + + < < − + +

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• Figure (fig 13) shows

Figure (fig 13) shows coulomb oscillations coulomb oscillations

• ver gate voltage
• ver gate voltage

range range

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• Figure (fig 14) shows

Figure (fig 14) shows the Id the Id-

• Vgs

Vgs characteristics for a characteristics for a SET having C SET having Cs

s=

=C Cd

d=1

=1 aF aF, Cg=3 , Cg=3 aF aF and and R Rt

t=10

=10 M MΩ Ω

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• Figure (fig 15) shows a SET inverter

Figure (fig 15) shows a SET inverter

• Simulations are performed using SPICE

Simulations are performed using SPICE

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• Logic circuits with single

Logic circuits with single-

• electron transistors

electron transistors

• Bias conditions for

Bias conditions for SETs SETs (to turn (to turn SETs SETs on)

• n)
• Figure (fig 16) shows a SET circuit where the SET is used as a

Figure (fig 16) shows a SET circuit where the SET is used as a pull up device pull up device

] 2 1 [ ] 2 1 [ V at ] 2 1 [ : hence zero, around voltage drain

• source

a at even

• n

turned be must SETs ,

, ds , ,

n C e V V n C e V V n C e V V V V V V V V V V V

g ds gs g dd up ON g g gs ds dd up ON g gs OUT up ON g gs OUT dd ds

+ + = + + = ⇒ = + = + − = − = − =

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• Conditions to turn

Conditions to turn SETs SETs off

• ff
• Design scheme

Design scheme

• Figure (fig 19) is a schematic of SET logic circuits

Figure (fig 19) is a schematic of SET logic circuits

• SET logic tree consists of pull

SET logic tree consists of pull-

• down

down SETs SETs only

• nly
• Clock Low:

Clock Low: precharge precharge period, load capacitor is charged regardless period, load capacitor is charged regardless

• f inputs of
• f inputs of SETs

SETs

• Clock High: Evaluation period, pull

Clock High: Evaluation period, pull-

• down device is turned on, logic

down device is turned on, logic state of the output will be determined depending on the inputs state of the output will be determined depending on the inputs

• (similar to CMOS dynamic logic)

(similar to CMOS dynamic logic)

) ( 2 ) ( 2 : be to required is V , V at

ds gs s g ds s g

C C e V C C e + < < + − =

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

Application of single electron devices to Application of single electron devices to logic circuits logic circuits

• Figure (fig 20) shows a 4

Figure (fig 20) shows a 4-

• input XOR made

input XOR made with with SETs SETs

• Figure (fig 21) shows the simulation results

Figure (fig 21) shows the simulation results