single-cycle (fjnish) / pipelining 0 1 Changelog 29 September - PowerPoint PPT Presentation

single-cycle (fjnish) / pipelining 0 1

Changelog 29 September 2020: rephrase questions on stage walkthrough slides 29 September 2020: make stage walkthrough partial circuits more complete 1

last time data memory operation accesses same data as instruction memory write at end of cycle if write enable signal set single-cycle CPU timing conceptual division into stages non-writing components compute/read as they get inputs writing components act at rising edge of clock building processors with MUXes (1) fjgure out what needs to happen for each instruction (2) place MUXes to make decision based on type of instruction 2

some linking/ISAHW notes (1) JMP instruction, etc.: takes an address relocations fjll in that address not the machine code at that address needs adjustment when combining object fjles into executable relocations generally don’t change machine code size 3

some linking/ISAHW notes (2) movq 0x1234(%rax,%rbx,8), %rcx … common error: missing memory access? common error: addition + multiplication not before memory access 4 reads from memory at address RAX + RBX × 8 + 0x1234

some linking/ISAHW notes (3) mov %X, %Y add %A, %Y mov %Y, %X add %B, %X mov %C, %Y add %A, %X add %B, %X mov %C, %Y 5

SEQ: instruction fetch read instruction memory at PC split into seperate wires: icode:ifun — opcode rA, rB — register numbers valC — call target or mov displacement compute next instruction address: valP — PC + (instr length) 6

instruction fetch add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 7

SEQ: instruction “decode” read registers valA, valB — register values 8

instruction decode (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: for which instructions would there be a problem ? nop , addq , mrmovq , rmmovq , jmp , pushq %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 9

instruction decode (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: for which instructions would there be a problem ? nop , addq , mrmovq , rmmovq , jmp , pushq %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 9

nop , addq , mrmovq , rmmovq , jmp , pushq of these: only pushq instruction decode (1) xor/and rA rB ALU aluA aluB valE 8 0 add/sub of instr.) (function 0xF write? function of opcode PC+9 instr. length + valP exercise: for which instructions would there be a problem ? %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 9

SEQ: srcA, srcB always read rA, rB? Problems: push rA pop call ret book: extra signals: srcA, srcB — computed input register MUX controlled by icode 10

SEQ: possible registers to read call , ret icode logic function F (none) %rsp rB srcB MUX %rsp rA pushq , popq %rsp none? rB instruction rA rmmovq , OP q rB none mrmovq none rA cmovCC , rrmovq none none halt , nop , j CC , irmovq srcB srcA 11

SEQ: possible registers to read call , ret icode logic function F (none) %rsp rB srcB MUX %rsp rA pushq , popq %rsp none? rB instruction rA rmmovq , OP q rB none mrmovq none rA cmovCC , rrmovq none none halt , nop , j CC , irmovq srcB srcA 11

instruction decode (2) add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 12

SEQ: execute perform ALU operation (add, sub, xor, and) valE — ALU output read prior condition codes Cnd — condition codes based on ifun (instruction type for jCC/cmovCC) write new condition codes 13

using condition codes: cmov ( always ) 1 ( le ) SF | ZF ( l ) SF cc (from instr) rB 0xF dstE NOT 14

execute (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions would there be a problem ? nop , addq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 15

execute (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions would there be a problem ? nop , addq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 15

SEQ: ALU operations? no, constants: (rsp +/- 8) computed ALU input values extra signals: aluA, aluB ret call popq pushq rmmovq ALU inputs always valA, valB (register values)? mrmovq valC valA aluA MUX no, inputs from instruction: (Displacement + rB) 16

execute (2) add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 17

SEQ: Memory read or write data memory valM — value read from memory (if any) 18

memory (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions would there be a problem ? nop , rmmovq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 19

memory (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions would there be a problem ? nop , rmmovq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 19

SEQ: control signals for memory read/write — read enable? write enable? Addr — address mostly ALU output special cases (need extra MUX): popq , ret Data — value to write mostly valA 20 special cases (need extra MUX): call

memory (2) add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 21

SEQ: write back write registers 22

write back (1) function ALU aluA aluB valE 8 0 add/sub xor/and (function of instr.) write? of opcode rA PC+9 instr. length + valP textbook convention: E used for storing ALU results (e.g. add) M used for storing memory results (e.g. rmmovq) (you don’t have to do this…) exercise: which of these instructions would there be a problem ? nop , irmovq , mrmovq , rmmovq , addq , popq rB %rsp PC Data Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM] Mem. 0xF ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp %rsp 0xF 23

write back (1) function ALU aluA aluB valE 8 0 add/sub xor/and (function of instr.) write? of opcode rA PC+9 instr. length + valP textbook convention: E used for storing ALU results (e.g. add) M used for storing memory results (e.g. rmmovq) (you don’t have to do this…) exercise: which of these instructions would there be a problem ? nop , irmovq , mrmovq , rmmovq , addq , popq rB %rsp PC Data Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM] Mem. 0xF ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp %rsp 0xF 23