single-cycle (fjnish) / pipelining 0 1 Changelog 29 September - - PowerPoint PPT Presentation

single-cycle (fjnish) / pipelining 0

1

Changelog

29 September 2020: rephrase questions on stage walkthrough slides 29 September 2020: make stage walkthrough partial circuits more complete

1

last time

data memory operation

accesses same data as instruction memory write at end of cycle if write enable signal set

single-cycle CPU timing

conceptual division into stages non-writing components compute/read as they get inputs writing components act at rising edge of clock

building processors with MUXes

(1) fjgure out what needs to happen for each instruction (2) place MUXes to make decision based on type of instruction

2

some linking/ISAHW notes (1)

JMP instruction, etc.: takes an address relocations fjll in that address

not the machine code at that address needs adjustment when combining object fjles into executable

relocations generally don’t change machine code size

3

some linking/ISAHW notes (2)

movq 0x1234(%rax,%rbx,8), %rcx … reads from memory at address RAX + RBX × 8 + 0x1234

common error: missing memory access? common error: addition + multiplication not before memory access

4

some linking/ISAHW notes (3)

mov %X, %Y add %A, %Y mov %Y, %X add %B, %X mov %C, %Y add %A, %X add %B, %X mov %C, %Y

5

SEQ: instruction fetch

read instruction memory at PC split into seperate wires:

icode:ifun — opcode rA, rB — register numbers valC — call target or mov displacement

compute next instruction address:

valP — PC + (instr length)

6

instruction fetch

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

7

SEQ: instruction “decode”

read registers

valA, valB — register values

8

instruction decode (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

exercise: for which instructions would there be a problem ? nop, addq, mrmovq, rmmovq, jmp, pushq

9

instruction decode (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

exercise: for which instructions would there be a problem ? nop, addq, mrmovq, rmmovq, jmp, pushq

9

instruction decode (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

exercise: for which instructions would there be a problem ? nop, addq, mrmovq, rmmovq, jmp, pushq of these: only pushq

9

SEQ: srcA, srcB

always read rA, rB? Problems:

push rA pop call ret

book: extra signals: srcA, srcB — computed input register MUX controlled by icode

10

SEQ: possible registers to read

instruction srcA srcB halt, nop, jCC, irmovq none none cmovCC, rrmovq rA none mrmovq none rB rmmovq, OPq rA rB call, ret none? %rsp pushq, popq rA %rsp MUX srcB

rB %rsp

(none)

F

logic function icode

11

SEQ: possible registers to read

instruction srcA srcB halt, nop, jCC, irmovq none none cmovCC, rrmovq rA none mrmovq none rB rmmovq, OPq rA rB call, ret none? %rsp pushq, popq rA %rsp MUX srcB

rB %rsp

(none)

F

logic function icode

11

instruction decode (2)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

12

SEQ: execute

perform ALU operation (add, sub, xor, and)

valE — ALU output

read prior condition codes

Cnd — condition codes based on ifun (instruction type for jCC/cmovCC)

write new condition codes

13

using condition codes: cmov

(always) 1 (le) SF | ZF (l) SF

cc

(from instr) rB 0xF dstE

NOT

14

execute (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

exercise: which of these instructions would there be a problem ? nop, addq, mrmovq, popq, call,

15

execute (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

exercise: which of these instructions would there be a problem ? nop, addq, mrmovq, popq, call,

15

SEQ: ALU operations?

ALU inputs always valA, valB (register values)? no, inputs from instruction: (Displacement + rB)

MUX

aluA

valA valC

mrmovq rmmovq

no, constants: (rsp +/- 8)

pushq popq call ret

extra signals: aluA, aluB

computed ALU input values

16

execute (2)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

17

SEQ: Memory

read or write data memory

valM — value read from memory (if any)

18

memory (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

exercise: which of these instructions would there be a problem ? nop, rmmovq, mrmovq, popq, call,

19

memory (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

exercise: which of these instructions would there be a problem ? nop, rmmovq, mrmovq, popq, call,

19

SEQ: control signals for memory

read/write — read enable? write enable? Addr — address

mostly ALU output special cases (need extra MUX): popq, ret

Data — value to write

mostly valA special cases (need extra MUX): call

20

memory (2)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

21

SEQ: write back

write registers

22

write back (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP textbook convention: E used for storing ALU results (e.g. add) M used for storing memory results (e.g. rmmovq) (you don’t have to do this…)

exercise: which of these instructions would there be a problem ? nop, irmovq, mrmovq, rmmovq, addq, popq

23

write back (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP textbook convention: E used for storing ALU results (e.g. add) M used for storing memory results (e.g. rmmovq) (you don’t have to do this…)

exercise: which of these instructions would there be a problem ? nop, irmovq, mrmovq, rmmovq, addq, popq

23

write back (1)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP textbook convention: E used for storing ALU results (e.g. add) M used for storing memory results (e.g. rmmovq) (you don’t have to do this…)

exercise: which of these instructions would there be a problem ? nop, irmovq, mrmovq, rmmovq, addq, popq

23

SEQ: control signals for WB

two write inputs — two needed by popq

valM (memory output), valE (ALU output)

two register numbers

dstM, dstE

write disable — use dummy register number 0xF

MUX

dstE

rB F %rsp

24

write back (2a)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

25

write back (2b)

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

26

SEQ: Update PC

choose value for PC next cycle (input to PC register)

usually valP (following instruction) exceptions: call, jCC, ret

27

PC update

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF Stat

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length + valP

28

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

29

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

29

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

29

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

30

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

30

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

31

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

32

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

33

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

34

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

35

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

36

circuit: setting MUXes

PC

Instr. Mem.

register fjle

srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]

Data Mem.

ZF/SF

Data in Addr in Data out

valC

0xF 0xF %rsp %rsp 0xF 0xF %rsp rA rB

ALU

aluA aluB valE 8 add/sub xor/and (function

• f instr.)

write? function

• f opcode

PC+9

instr. length +

8 9

PC+2 M[PC+1]

rA=8 rB=9 R[8] R[9] aluA + aluB M[PC+2]

add

MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for mrmovq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for jle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for cmovle? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for popq? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call?

37

Human pipeline: laundry

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors whites whites whites colors colors colors sheets sheets sheets

38

Human pipeline: laundry

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors whites whites whites colors colors colors sheets sheets sheets

38

Waste (1)

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors sheets sheets sheets

wasted time! wasted time!

39

Waste (1)

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors sheets sheets sheets

wasted time! wasted time!

39

Waste (2)

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors sheets sheets sheets

40

Latency — Time for One

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors sheets sheets sheets

pipelined latency (2.1 h)

colors colors colors

normal latency (1.8 h)

41

Latency — Time for One

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors sheets sheets sheets

pipelined latency (2.1 h)

colors colors colors

normal latency (1.8 h)

41

Latency — Time for One

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors sheets sheets sheets

pipelined latency (2.1 h)

colors colors colors

normal latency (1.8 h)

41

Throughput — Rate of Many

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors sheets sheets sheets

time between fjnishes (0.83 h) load h loads/h time between starts (0.83 h)

42

Throughput — Rate of Many

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors sheets sheets sheets

time between fjnishes (0.83 h) 1 load 0.83h = 1.2 loads/h time between starts (0.83 h)

42

Throughput — Rate of Many

Washer Dryer Folding Table

11:00 12:00 13:00 14:00

whites whites whites colors colors colors sheets sheets sheets

time between fjnishes (0.83 h) 1 load 0.83h = 1.2 loads/h time between starts (0.83 h)

42