Silicon Compilers - Version 2.0 Andreas Olofsson Program Manager, DARPA/MTO I nternational Symposium on Physical Design March 25-28, Monterey, CA Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
A Brief History of EDA 2 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
ENI AC : A world without Moore’s Law https://en.wikipedia.org/wiki/ENIAC Source: https://en.wikipedia.org/wiki/ENIAC • • 20,000 vacuum tubes • 50% uptime First all electric computer • • • 27 tons 2 week compilations 357 mults/sec • • $6.7M (adjusted) 5M solder joints! 3 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
The modern miracle of Moore’s Law https://www.allpar.com/history https://en.wikipedia.org/wiki/ENIAC https://en.wikipedia.org/wiki/Titan_(supercomputer) https://www.caranddriver.com/chevrolet/cruze 1946 Today 1946 Today Speed, mph (S) 78 102 Speed, OPS/S (S) 359 17.9e15 Efficiency, mpg (E) 14.6 22 OPS/W (E) 0.002 2e9 Cost, $K (C) 1.7 27 Cost, $M (C) 6.5 97 (S * E ) / C 669 83 (S * E ) / C 0.11 3e23 4 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
1970’s: Heroic human efforts Source: https://en.wikipedia.org/wiki/Intel_400 • Intel 4004 (1971-1981) • 10-um feature size Source: http://www.computerhistory.org/revolution/artifact/287/1614 Rubylith operators • 2,300 transistors 5 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
1980’s: The birth of modern EDA Synthesis Place and Route Source: https://en.wikipedia.org/wiki/Logic_synthesis Source: http://venividiwiki.ee.virginia.edu/mediawiki/ Layout Systems Framework Source: http://opencircuitdesign.com/magic/ Source: Introduction to VLSI Source: https://en.wikipedia.org/wiki/Intel_80386 systems by Carver Mead • Intel 80386 (1985-2007) Birth of Modern EDA • 1-um feature size Synopsys Cadence Mentor Graphics • 275,000 transistors 6 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
1990’s-Today: Managing complexity Source: https://nvidianews.nvidia.com/file?fid= 59129280a138351b9447113c It took several thousand engineers several years to create, at an approximate development cost of $3 billion. –Jensen Huang • NVIDIA V100 (2017-) • 0.012um feature size • 21,000,000,000 transistors Death by a million papercuts… correctness, application performance, IP integration, power management, firmware, system integration, wire delays, place and route optimization, clocking, packaging, signal integrity, triple patterning, antenna effects, ESD, muti voltage, power gating, multi threshold, area minimization, routing congestion, on-chip variability, self heating, electro migration, SEUs, signal integrity, power delivery networks, decoupling, model accuracy, abstraction layers, low voltage operations, cooling, security, formal proofs, design for test, metal density rules, OPC concerns, timing convergence, yield optimization, static and dynamic power minimization, scan compression, memory BIST, area minimization… 7 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
Has EDA failed to keep up with Moore’s Law? 10B 100M 1M 10K 100 8 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
It’s not that simple…. Epiphany-V Value Process TSMC 16FF+ Transistors 4.5B Die Area 117 mm 2 Source: Adapteva “Server Farm”: Flip Chip Bumps 3,460 • One 2010 Dell PowerEdge I/O Signals 1,040 T610 with a quad-core Xeon Clock Domains 1,152 5500 and 32GB DDR3 • One RTL to GDS EDA license Voltage Domains 2,052 • 12 month design, 24hr spins Frequency 500Mhz* Source: Dell 32 Performance 2 TFLOPS Designer Responsibility Man-Hours 64 bit Performance 1 TFLOPS Contractor A FPU 200 Memory Bandwidth 16 TB/sec Contractor B Verification 200 NOC Bandwidth 0.75 TB/sec Contractor C EDA Services 112 Typical Power ~ 10W Ola Jeppsson Simulator/SDK 500 Minimum Power 1mW Andreas Olofsson Remainder 4,100 9 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
My personal EDA interaction over 20 years E5 16nm 1024 CPUs E4 4.5B xtors Transistors/Hour 1Eng* 12M 28nm adapteva 64 CPUs 200M xtors E3 3Eng* 3M 65nm E2 16 CPUs 65nm 50M xtors 16 CPUs 3Eng* 3M 50M xtors E1 1Eng* 2M 65nm 16 CPUs AD9020 TS101 50M xtors 350nm 130nm 1Eng* 16M TS201 1 CPU 1500X Engineering 1 CPU < 1M xtors 130nm 45M xtors 1Eng* 3M Productivity Improvement 1 CPU 30Eng* 24M 50M xtors 100Eng* 24M 1999 2007 2016 http://www.analog.com http://www.adapteva.com 10 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited) http://www.ieee.org
My view : EDA needs to move to 100% automation 1T Automation 10 11 Westmere 1.00 100,000,000,000 Pentium4 10 10 10,000,000,000 0.90 486 10 9 1B 1,000,000,000 0.80 10 8 100,000,000 0.70 8088 10 7 10,000,000 0.60 10 6 1M 1,000,000 4004 0.50 10 5 100,000 0.40 10 4 10,000 0.30 10 3 1,000 1K Transistors 0.20 10 2 100 0.10 10 1 10 10 0 1 0.00 1 1960 1970 1980 1990 2000 2010 2020 Automation Transistors Image source: Intel 11 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
Making the case for democratizing EDA • “Supercomputing for everyone“ • $99 FPGA + 18 CPU cores @ 5W • No NDAs! • Open source and open access • $900K raised in 30 days • First ever crowd funded chip • 10,000 boards shipped Metric Before After Boost Customers 5 10,000 2000x • 100+ community publications Universities 1 200 200x Site traffic 20 1,000 50x Twitter Followers 20 6,000 50x Open works! Publications 2 150 75X Govt customers 2 10 5x 12 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
Electronic Resurgence I nitiative (ERI ) I ntroduction 13 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
Electronics Resurgence Initiative: Introduction 2025 – 2030 Page 3 I nvestments National Electronics Capability • Design Industry/government partnerships How do we lower the design barrier to specialization? Design Architectures Materials • Architectures How do we manage the complexity of Andreas Tom Rondeau/ Y .K. Chen/ specialization with new architectures? Olofsson Wade Shen Linton Salmon • Materials JUMP + Traditional Programs How do we integrate new materials for specialized functions? $141M in Current Efforts (FY18) $75M of New Page 3 Funding (FY18) Resting on a foundation of existing research programs are newly formulated thrusts that all sum into the Electronics Research Initiative, a four-year push with anticipated annual investments in the $200 million range. 14 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
Recent DARPA investments and momentum 2016 2017 2019 2018 Electronics Resurgence I nitiative 11/2015 N-ZERO Today Kickoff 4/2016 JUMP CRAFT University Driven Kickoff 6/2016 CHIPS Approved Page 3 I nvestments 8/22/2016 JUMP Industry Driven 1/2017 Approved L2M Approved • N-ZERO • CRAFT • CHI PS 4/2017 • L2M SSITH • HI VE BAA Released • SSI TH OTAs signed in 12 month period Qualcomm Rambus 4/2017 XILINX Micron Intel HIVE Keysight Flexlogix Kickoff Traditional NVIDIA Technologies Cadence Technologies, Inc Programs 15 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
ERI “Page 3” Program Service Announcement Materials & I ntegration • Monolithic Integration of an SoC in Three Dimensions (3DSoC) , Linton Salmon • Framework for Novel Compute (FRANC), Y .K. Chen Architecture: • Software Defined Hardware (SDH), Wade Shen • Domain-Specific System on Chip (DSSoC), Thomas Rondeau Design • Intelligent Design of Electronic Assets (IDEA), Andreas Olofsson • Posh Open Source Hardware (POSH), Andreas Olofsson 16 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
Building a Hardware Compiler at DARPA 17 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
We are building a universal hardware compiler Modern Software A Universal No Human In the Compilation Loop Hardware Compiler Source Code, Software compilers moved beyond Schematics, humans in the loop 50 years ago! Constraints POSH Qualified Synthesis/Generators Source Code Knowledge Circuits Driven Domain I DEA Qualified Specific Intelligent No Human In Circuits Models the Loop Layout Engine Partial layout Qualified Linker Layout Final layout A no-human in the loop hardware compiler addresses cost, schedule, resource, trust challenges in current SoC design cycle. 18 Distribution Statement “A” (Approved for Public Release, Distribution Unlimited) Source: mattturck.com/bigdata2017
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