Scheduling Marcel Kneib marcel.kneib@posteo.de Hochschule RheinMain - - PowerPoint PPT Presentation

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Scheduling Marcel Kneib marcel.kneib@posteo.de Hochschule RheinMain - - PowerPoint PPT Presentation

Feb 08, 2024 180 likes •346 views

User-Level CPU Inheritance Scheduling Marcel Kneib marcel.kneib@posteo.de Hochschule RheinMain Jonas Reininger jonas.reininger@gmail.com Hochschule RheinMain Introduction Scheduling in user-level Hierarchy of schedulers

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SLIDE 1

User-Level CPU Inheritance Scheduling

Marcel Kneib – marcel.kneib@posteo.de – Hochschule RheinMain Jonas Reininger – jonas.reininger@gmail.com – Hochschule RheinMain

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SLIDE 2

Marcel Kneib, Jonas Reininger 2/16 Hochschule RheinMain

  • Scheduling in user-level
  • Hierarchy of schedulers
  • Threads can act as schedulers for other

threads

Introduction

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SLIDE 3

Marcel Kneib, Jonas Reininger 3/16 Hochschule RheinMain

  • More flexibility
  • Smaller trusted code base
  • Meeting different scheduling requirements
  • Reduce costs

Benefits

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SLIDE 4

Marcel Kneib, Jonas Reininger 4/16 Hochschule RheinMain

Concept

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SLIDE 5

Marcel Kneib, Jonas Reininger 5/16 Hochschule RheinMain

H M L Priority Inheritance

Priority inversion

H M L

Priority inheritance

H

Mars Pathfinder, 1997

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SLIDE 6

Marcel Kneib, Jonas Reininger 6/16 Hochschule RheinMain

Root Scheduler:

– H: Real-time

  • RM1: 50% CPU time
  • RM2: 25% CPU time

– M: Timesharing

  • LS1: available CPU time

– L: Background

  • RR1: available CPU time
  • RR2: available CPU time

Test Environment

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SLIDE 7

Marcel Kneib, Jonas Reininger 7/16 Hochschule RheinMain

Test

  • 1. RM1 starts consuming 50% CPU time periodically
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SLIDE 8

Marcel Kneib, Jonas Reininger 8/16 Hochschule RheinMain

Test

  • 2. RR1 begins to consume alle the CPU time it can get
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SLIDE 9

Marcel Kneib, Jonas Reininger 9/16 Hochschule RheinMain

Test

  • 3. RR2 begins with the same priority as RR1
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SLIDE 10

Marcel Kneib, Jonas Reininger 10/16 Hochschule RheinMain

Test

  • 4. LS1 begins to steal all available CPU time
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SLIDE 11

Marcel Kneib, Jonas Reininger 11/16 Hochschule RheinMain

Test

  • 5. RM2 starts consuming 25% of the CPU time periodically
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SLIDE 12

Marcel Kneib, Jonas Reininger 12/16 Hochschule RheinMain

Test

  • 6. LS1 finishes
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SLIDE 13

Marcel Kneib, Jonas Reininger 13/16 Hochschule RheinMain

Problems

  • Dispatcher costs

– iteration through list or tree

  • Context switch costs

– approx. one additional context switch

  • Threads running in one single address space

– no memory protection – not isolated

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SLIDE 14

Marcel Kneib, Jonas Reininger 14/16 Hochschule RheinMain

Problems

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SLIDE 15

Marcel Kneib, Jonas Reininger 15/16 Hochschule RheinMain

Conclusion

  • More flexibility with negligible overhead (in Test

Environment)

  • If per-context-switch-costs are low, CPU Inheritance

Scheduling makes sense even in microkernels

  • Scheduling hierarchy depth should be limited
  • Sample implementation is based on user-thread

library

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SLIDE 16

Questions?

Marcel.Kneib@posteo.de Jonas.Reininger@gmail.com