RV-IOV: Tethering RISC-V Processors via Scalable I/O Virtualization - - PowerPoint PPT Presentation

RV-IOV: Tethering RISC-V Processors via Scalable I/O Virtualization

Luis Vega and Michael B. Taylor Bespoke Silicon Group University of Washington

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Berkeley’s Tethered Rocket core

The host system provide support for:

• Memory subsystem
• Load binaries
• Start/terminate programs
• System call offloading (w/ PK)
• Emulate peripheral devices (w/ OS)

Rocket Core Host System

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Berkeley’s Rocket Emulation Platforms

Zybo Zedboard ZC706

https://github.com/ucb-bar/fpga-zynq

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Challenge #1: ASIC prototyping

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I/O Host Mem Total # 36 298 334 I/O I/O I/O I/O QFN QFP WL-CSP BGA FC ~68 ~300 ~1k ~2k Total package I/O Package cost ($) Total Package I/O ~~ 3 x Data-I/O (power supply reasons)

Challenge #2: FPGA (LUT) resources

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Solution: RV-IOV

• RV-IOV decouples the Rocket core from the host processor
• RV-IOV allows multiple Rocket cores to be implemented on

external ASIC prototypes or FPGA emulation boards

• RV-IOV extends Rocket supported FPGA boards

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RV-IOV system level

Switch RV-IOV

Host (FPGA)

Arbiter Shared interconnect RV-IOV

Client (FPGA or ASIC)

Switch RV-IOV Rocket system (1) RV-IOV Rocket system (n)

Virtual I/O Physical I/O Scalable

Host Processor

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Rocket core

RV-IOV - internal operations

• 1. Memory serialization
• 2. Stream interleaving

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Host

RV-IOV

Mem

single stream

RV-IOV - memory serialization

• AXI4 memory protocol is

serialized

• Merge write/read memory

channels into a single bidirectional channel

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write Memory serializer read Rocket core

{aw, w, b} {ar, r} Mem host

memory host

RV-IOV - stream interleaving

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• Interleave memory and host packets
• Round robin fashion
• Flow control: credit protocol
• Maximize throughput
• Avoid deadlocks

Stream Interleaving memory host single stream

RV-IOV FPGA evaluation

Zedboard

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DoubleTrouble

DoubleTrouble is an Open Source Emulation Platform

https://bjump.org

RV-IOV FPGA evaluation

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One hop system Two hop system

Rocket core configuration

• 5 stage, in-order, scalar processor
• Double precision, floating point
• I-cache: 16 KB 4-way assoc.
• D-cache: 16 KB 4-way assoc.
• RV64G ISA

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Results

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Conclusion

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• RV-IOV increases implementation flexibility for both ASIC and

FPGA Rocket designs

• RV-IOV allows larger Rocket core configurations, i.e. multi-

core and powerful accelerators

• RV-IOV will be available @ https://bjump.org/rv_iov

Questions?

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