Resource Allocation for Hardware Implementations of Map Richard - - PowerPoint PPT Presentation

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Resource Allocation for Hardware Implementations of Map Richard - - PowerPoint PPT Presentation

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Resource Allocation for Hardware Implementations of Map Richard Townsend Martha A. Kim Stephen A. Edwards Columbia University ASBD Workshop, June 15, 2014 Functional Programs to Functional Hardware Functional program (Haskell) Compiler

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SLIDE 1

Resource Allocation for Hardware Implementations of Map

Richard Townsend Martha A. Kim Stephen A. Edwards

Columbia University

ASBD Workshop, June 15, 2014

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SLIDE 2

Functional Programs to Functional Hardware

Functional program (Haskell) Compiler Circuit (Verilog)

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SLIDE 3

Functional Programs to Functional Hardware

Map f [x1,x2,...,xn]

This Talk

?

Ordered List

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SLIDE 4

Functional Programs to Functional Hardware

Map f [x1,x2,...,xn]

This Talk

?

Ordered List

fold scan

Order Dependent

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SLIDE 5

Functional Map vs. MapReduce

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SLIDE 6

Functional Map vs. MapReduce

(0,0) (0,1) (0,2) (0,3) (1,0) (1,1) (1,2) (1,3) (2,0) (2,1) (2,2) (2,3) (3,0) (3,1) (3,2) (3,3)

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SLIDE 7

Functional Map vs. MapReduce

(0,0) (0,1) (0,2) (0,3) (1,0) (1,1) (1,2) (1,3) (2,0) (2,1) (2,2) (2,3) (3,0) (3,1) (3,2) (3,3)

Ordered

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SLIDE 8

Functional Map vs. MapReduce

(0,0) (0,1) (0,2) (0,3) (1,0) (1,1) (1,2) (1,3) (2,0) (2,1) (2,2) (2,3) (3,0) (3,1) (3,2) (3,3)

Ordered Unordered

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SLIDE 9

Structure of a Hardware Implementation

f

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SLIDE 10

Structure of a Hardware Implementation

f f f f f

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SLIDE 11

Structure of a Hardware Implementation

f f f f f

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SLIDE 12

Structure of a Hardware Implementation

f f f f f x1 x2 x3 x4 x5 x6 x7 x8 x9 x10

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SLIDE 13

Structure of a Hardware Implementation

f f f f f x1 x2 x3 x4 x5 x6 x7

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SLIDE 14

Structure of a Hardware Implementation

f f f f f x1 x2 x3 x4 x5 x6 x7 x8 x9 x10

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SLIDE 15

Structure of a Hardware Implementation

f f f f f x6 x7 x8 x9 x10 f (x1) x2 x4 x5 f (x3)

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SLIDE 16

Structure of a Hardware Implementation

f f f f f f (x1) x2 x4 x5 f (x3) x6 x7 x8 x9 x10

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SLIDE 17

Structure of a Hardware Implementation

f f f f f x2 x4 x5 f (x3) x6 x7 x8 x9 x10 f (x1)

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SLIDE 18

Structure of a Hardware Implementation

f f f f f x2 x4 x5 f (x3) x6 x7 x8 x9 x10 f (x1) f (x7)

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SLIDE 19

Structure of a Hardware Implementation

f f f f f x2 x4 x5 f (x3) x6 x7 x8 x9 x10 f (x1) f (x7) still processing

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SLIDE 20

Structure of a Hardware Implementation

f f f f f x2 x4 x5 f (x3) x6 x7 x8 x9 x10 f (x1) f (x7) still processing stuck in buffer

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SLIDE 21

Structure of a Hardware Implementation

f f f f f x2 x4 x5 f (x3) x6 x7 x8 x9 x10 f (x1) f (x7) still processing stuck in buffer holding and stalling

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SLIDE 22

Structure of a Hardware Implementation

f f f f f

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SLIDE 23

Structure of a Hardware Implementation

f f f f f More Functional Units (Parallelism) More Buffers (Utilization)

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SLIDE 24

Multiple Possible Configurations...Which to Choose?

Area = 15

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Multiple Possible Configurations...Which to Choose?

Area = 15 Buffers 50% size of func. unit

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SLIDE 26

Multiple Possible Configurations...Which to Choose?

Area = 15

f f f f f f f f f f f f f f f

15 Functional Units

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SLIDE 27

Multiple Possible Configurations...Which to Choose?

Area = 15

f

28 Buffers

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SLIDE 28

Multiple Possible Configurations...Which to Choose?

Area = 15

f f f f f

20× 1

2 = 10

5

f f f

24× 1

2 = 12

3

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SLIDE 29

Workload Structure

f f f

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Workload Structure

f f f

Best-case

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SLIDE 31

Workload Structure

f f f

Best-case

Time f f f

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SLIDE 32

Workload Structure

f f f

Best-case

Time f f f

Average-case

?

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SLIDE 33

Workload Structure

f f f

Best-case

Time f f f

Average-case

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Worst-case

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SLIDE 34

Workload Structure

f f f

Best-case

Time f f f

Average-case

?

Worst-case

f f f

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SLIDE 35

Workload Structure

f f f

Best-case

Time f f f

Average-case

?

Worst-case

f f f

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SLIDE 36

Optimal Resource Allocation

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

Simulator Results

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Optimal Resource Allocation

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

Simulator Results 2x speedup

Maximizing Functional Units

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SLIDE 38

Optimal Resource Allocation

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

Simulator Results 3x speedup

Maximizing Buffers

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SLIDE 39

Optimal Resource Allocation

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

f f f f f

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Optimal Resource Allocation

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

f f f f f

Fewer Buffers Slower

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SLIDE 41

Why Are There Multiple Optima?

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time

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Why Are There Multiple Optima?

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time

12 5

7 10

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SLIDE 43

Why Are There Multiple Optima?

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time

12 5

7 10 11 6 6 11

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SLIDE 44

Performance Scales with Area

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10 20 30 40 50 60 Completion Time Total Area

Ideal Minimum

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Performance Scales with Area

0% 20% 40% 60% 80% 100% 10 20 30 40 50 60 Completion Time 10 20 30 10 20 30 40 50 60 Buffers Slots / Functional Unit 2 4 6 8 10 10 20 30 40 50 60 Functional Units Total Area

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SLIDE 46

Performance Scales with Area

0% 20% 40% 60% 80% 100% 10 20 30 40 50 60 Completion Time 10 20 30 10 20 30 40 50 60 Buffers Slots / Functional Unit 2 4 6 8 10 12 10 20 30 40 50 60 Functional Units Total Area

f f

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SLIDE 47

Conclusions

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

Area trade-off is important...

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SLIDE 48

Conclusions

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

Area trade-off is important...

f f f f f f f f

?

...and non-obvious

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SLIDE 49

Conclusions

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

Area trade-off is important...

f f f f f f f f

?

...and non-obvious

f f f f f x1 x2 x3 x4 x5 x6 x7 x8 x9 x10

Model helps explore design space

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SLIDE 50

Conclusions

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

Area trade-off is important...

f f f f f f f f

?

...and non-obvious

f f f f f x1 x2 x3 x4 x5 x6 x7 x8 x9 x10

Model helps explore design space

Synthesize Efficient Hardware Implementation of Map

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SLIDE 51

Conclusions

0% 20% 40% 60% 80% 100% 5 10 15 20 25 30 Completion Time 50 100 150 200 250 Buffer Slots per Functional Unit

Area trade-off is important...

f f f f f f f f

?

...and non-obvious

f f f f f x1 x2 x3 x4 x5 x6 x7 x8 x9 x10

Model helps explore design space

Synthesize Efficient Hardware Implementation of Map

Map Fold Scan

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10 20 30 40 50 60 Completion Time Total Area

Enhance our abstraction