Reducing Interpolant Circuit Size by Ad-Hoc Logic Synthesis and SAT-Based Weakening Gianpiero Cabodi Paolo Camurati Paolo Pasini Marco Palena Danilo Vendraminetto Politecnico di Torino Torino, Italy 1
Outline l Motivations & background l Craig interpolation in MC => Size bottleneck (>10 5 gates) l Highly redundant circuits, missing ad hoc reduction l Contribution l Ad HOC (fast) logic synthesis (based on known techniques) l SAT-based Weakening (and strenthening) with high compaction potential (strength/time for size) l Experimental results & Conclusions 2
Motivations & related works l Interpolation (ITP) still a major engine in UMC portfolio [McMillan CAV’03] l Other ITP usages l Formula/constraint synthesis in predicate abstr. l Scalability problem l ITPs are large and highly redundant l Previous efforts [Marques-Silva CHARME’05, D’Silva et al. VMCAI’08, Cabodi et al. FMSD’15, Rollini et al LPAR’13 (PeRIPLO)] l Proof reduction l Interpolant compaction 3
Background: Craig Interpolant for IMG in Unbounded MC Unroll k F T T T T T From To R k,bwd To+ 4
Interpolant: set view ∩ A(x,y) B(y,z) ∧ 5
Interpolant: set view A(x,y) B(y,z) ∧ I(y) 6
Craig Interpolant from refutation proof A B CNF clauses UNSAT problem (A ∧ B = 0) 7
Craig Interpolant from refutation proof A B Resolution graph Null clause 8
Craig Interpolant from refutation proof A B Unsatisfiable core Resolution graph resolution (A ∨ p) ( ¬ p ∨ B) (A ∨ B) Null clause 9
Craig Interpolant from refutation proof A B 1 Resolution AND-OR graph circuit I(Y) = Interpolant (A(X,Y),B(Y,Z)) Null clause 10
Craig Interpolant from refutation proof A B 1 Resolution AND-OR graph circuit A gate for each resolution node I(Y) = Interpolant (A(X,Y),B(Y,Z)) Null clause 11
Redundancy / Compaction |Interpolant| = O(|proof|) highly redundant => compaction l Reduce proof l Recycle-pivots, local transformations, proof restructure l Combinational logic synthesis l BDD/SAT-sweeping l Rewriting l Refactoring l Ad hoc logic synthesis l Logic synthesis using proof graph l ITE-based decompose & compact 12
Contributions l AD-hoc logic synthesis (rewrite/refactor) l Implemented/tuned for interpolants l Interpolant strength unchanged l Trade-off speed for optimality l Compaction by strenghtening/weakening l Gate Level Abstraction l Proof (core) based l Expensive (SAT needed) l Trade-off strength for size 13
Circuit graph decomposition y 1 1 I y N 14
Circuit graph decomposition 1 15
Circuit graph decomposition Macrogates 1 16
Circuit graph decomposition Macrogates 1 17
Circuit graph decomposition Cluster 1 18
Circuit graph decomposition 1 Cut 19
Circuit graph decomposition 1 Dominators 20
Circuit graph decomposition d 1 n d dominates n 21
Rewrite: direct ODC removal y 1 a f y N 22
Rewrite: direct ODC removal a y 1 f 1 g y N F(Y,a) = a ∧ g(Y,a) = a ∧ g(Y,1) 23
Rewrite: direct ODC removal y 1 a f 1 y N 24
Algorithm DirectOdcSimplify() forall clusters CL find node v ∈ cut(CL) with fanout(v) >1 in CL take u,t ∈ fanout(v) ∩ CL if (domG(t) dominates u) u <= constant // u is redundant 25
Rewrite: transitive ODC a y 1 f a y N 26
Rewrite: transitive ODC a y 1 f 1 y N 27
Refactor: search sharable term c c d a b 28
Refactor: search sharable term c c d a b 29
Refactor: search sharable term c a c b d 30
Refactor: search sharable term c a b d 31
Algorithm MacrogateRefactor() forall macrogates G forall nodes v ∈ cut(G) find AND(u,v) ∉ G such that u ∈ cut(G) refactor G using AND(u,v) 32
Experimental results l Implementation on PdTrav tool l HWMCC ’07 to ‘15 l ITPs stored on files from MC runs l Picked 87 instances l experiments also on ITPs from PeRIPLO (Sharygina’s group, Lugano) 33
Logic synthesis • Benchmark set (87 ITPs) • Size range: 4·10 5 – 8,5 ·10 6 gates • Average size: 2 ·10 6 gates • Experimental set-up • Time limit: 900 seconds • Memory limit: 8 GB Completed Average Average Benchmarks compaction rate execution time Balance 87 61.31 % 25.27 s ITP Simplify 68 83.06 % 421.06 s No Direct ODC 68 80.83 % 505.89 s No Refactoring 86 69.28 % 84.80 s No Transitive ODC 72 80.93 % 310.46 s ABC 31 94.96 % 568.98 s
Cumulative size
Cumulative time
ITP weakening by SAT GLA l GLA: Gate Level Abstraction l used here to abstract combinational circuit l SAT-based abstraction (PBA) l SAT(I ∧ B) => UNSAT CORE => abstract l Given cut var, monotonicity => existential quantification by constant substitution l NNF encoding l monotone w.r.t. all circuit nodes except Pis. 37
Interpolant weakening I(y) B(y,z) ∧ 38
Interpolant weakening I W (y) I(y) B(y,z) 39
Interpolant weakening I(y) B(y,z) ∧ 1 40
Interpolant weakening I(y) B(y,z) ∧ 1 UNSAT => CORE 41
Interpolant weakening I(y) B(y,z) ∧ 1 N N out of CORE 42
Interpolant weakening I(y) B(y,z) ∧ 1 N ABSTRACT 43
Interpolant weakening I(y, N ) B(y,z) ∧ 1 N EXTRA VARIABLE 44
Existential quantification NNF encoding NNF circuit monotone w.r.t. internal nodes Quantification by constant substitution ∃ N I(Y,N) = I(Y,1) 1. I(Y) => I NNF (Y) 2. SAT(I NNF (Y) ∧ B(Y,Z)) 3. I NNF => (uns. core, abstract, inject 1) => I NNF,weak 4. I NNF,weak => I weak 45
Interpolant strengthening ¬ I(y) A(x,y) ∧ Strengthening by weakening complement of interpolant w.r.t. A 46
SAT-based weakening • Benchmark set (87 circuits) • Size range: 4·10 5 – 8,5 ·10 6 gates • Average size: 2 ·10 6 gates • Experimental set-up • Time limit: 3600 seconds • Memory limit: 8 GB Completed Average Average Benchmarks compaction rate execution time A 72 82.24 % 902.33 s AB 63 97.99 % 1495.78 s ABAB 57 99.59 % 1649.79 s B 68 97.53 % 1324.51 s BA 67 98.03 % 1371.30 s BABA 60 99.56 % 1470.84 s
Cumulative size
Cumulative time
Conclusions l Contributions: l Adapting logic synthesis for fast/scalable ITP compaction l More expensive SAT-based compaction (weakening/strengthening) l Evaluation l Fast synthesis always used l Expensive weakening/strengthening l Avoid memory explosion (or time not critical) l Strength may impact on quality of result 50
Thank you! 51
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