Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA - - PowerPoint PPT Presentation

Institut für Technische Informatik Chair for Embedded Systems - Prof. Dr. J. Henkel Vorlesung im SS 2010

Reconfigurable and Adaptive Systems (RAS)

New Directions in FPGA Design

• A. Grudnitsky, L. Bauer, J. Henkel

Carbon Nanotube Based Architectures eFPGAs References

Outline

1

Carbon Nanotube Based Architectures Carbon Nanotubes A Field Programmable Carbon Nanotube Array 3D nFPGA2

2

eFPGA - Embedded FPGA eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 2

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

State of Semiconductor Fabrication

Higher integration requires smaller feature size → CMOS scaling Current feature size: 45nm - 32nm International Technology Roadmap for Semiconductors assesses developments in Semiconductor production and projects targets for future fabrication processes Next technology nodes:

22nm (ITRS: 2015, Intel announced for 2011) 16nm (ITRS: 2018)

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 3

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Problems With CMOS Scaling

Smaller feature size → more complex fabrication process Low yield

Non-visual defects cause electric failure, leave no physical remnant → very hard to test for Process variation

Increasing device failure probability during its lifetime (e.g. Electromigration) Size limit - transistors already only a few atoms thick - can’t scale down much further High manufacturing costs

Expensive equipment (e.g. Steppers) Clean room requirements

One solution: use new materials. Here: Carbon Nanotubes

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 4

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

The Carbon Nanotube (CNT)

[src: LBL07] [src: Ausman]

Graphene (deutsch: “Graphen”) - planar sheet of carbon atoms, bonded in a hexagonal lattice Carbon Nanotube: sheet of graphene wrapped into a tube

Few nm thick, up to several cm long

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 5

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Types of CNTs

TEM micrographs of SW and MW CNTs [src: Zettl]

Single-Walled CNTs (wall thickness 0.7nm - 2nm)

can be either metallic or semiconducting

Multi-Walled CNTs (wall thickness 10nm - 20nm, multiple concentric wall layers)

metallic

In this lecture: only Single Walled Carbon Nanotubes (SWCNT) (unique electric properties)

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 6

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Types of CNTs

TEM micrograph of MWCNT produced using Laser assisted chemical vapor deposition [src: Bondi] Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 7

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Properties of CNTs

Electrical

Depending on the chirality of the CNT (“angle under which the graphene sheet is rolled up”) a CNT is either metallic

• r semiconducting

Resistant to Electromigration

Thermal

High thermal conductivity along the tube Thermal insulation across the tube

High contact resistance for individual CNTs

use bundles of CNTs for interconnect

Other properties:

Very high mechanical strength Can be used for field emission - electron beam source

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 8

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT Manufacturing Methods

Catalyst enhanced Chemical Vapor Deposition (CCVD)

place catalyst particle on substrate pass carbon gas over wafer CNT grows

Arc discharge - arc induced between two rods and vaporizes one carbon rod. Vaporized carbon reforms into CNTs Laser ablation - similar principle as arc discharge - use laser to vaporize rod

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 9

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT Manufacturing Methods

Problem: stochastic process, can only bias towards a certain type of CNT (metallic or semiconducting)

Recent (end 2009) research has presented techniques to increase bias at up to > 90% towards the desired type of CNT Techniques to separate metallic from semiconducting CNTs exist

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 10

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT Field Effect Transistor

CNT FET [src: HH2009]

Same operation principle as silicon-based transistors Only the conducting channel is CNT based. Source, Drain, Gate can be produced with standard fabrication techniques Under ideal conditions: CNT FET can be up to > 10x faster, but: imperfections, parasitic capacitances, etc.

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 11

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT NRAM

[src: HH2009]

Trench with base electrode at bottom CNT suspended over trench

• ff: CNT hangs over trench, no contact to base electrode

→ very high junction resistance (no contact)

• n: CNT is bent into trench, contact with electrode → low

junction resistance (contact)

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 12

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT NRAM

but: does on state consume power to overcome elastic strain of CNT? No, van-der-Waals forces between CNT and electrode molecules keep CNT bent into trench Only state changes require energy Other properties:

No mechanical fatigue Naturally radiation hardened Resistant to mechanical shock, vibration Work in a wide temperature range (below room temp to 200◦C) Switching speed: 2GHz for 180nm process, expected to be much higher for smaller feature size

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 13

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT NRAM

but: does on state consume power to overcome elastic strain of CNT? No, van-der-Waals forces between CNT and electrode molecules keep CNT bent into trench Only state changes require energy Other properties:

No mechanical fatigue Naturally radiation hardened Resistant to mechanical shock, vibration Work in a wide temperature range (below room temp to 200◦C) Switching speed: 2GHz for 180nm process, expected to be much higher for smaller feature size

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 13

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT NRAM

Nanotube fabric suspended over embedded electrode. Bond pads on each side. [src: Ward] Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 14

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT Bundle Interconnect

Bundle of SWCNTs produced using laser ablation [src: Maser]

Current material for interconnect: Cu

Problems: Electromigration, grain-boundary scattering

Single CNTs have large contact resistance → use bundles

• f CNTs

Performance can be higher than Cu interconnect, esp. for longer distances

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 15

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Solid-Electrolyte Nanoswitch

[src: CDC2009] [src: Kaeriyama]

Not CNT based, but still a nano-scale device Solid Electrolyte (Cu2S) used as bridge between two metal layers Depending on voltage between metal layers, nanometer-scale metal bridge is grown (switch on) or shrunk (switch off) .

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 16

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Solid-Electrolyte Nanoswitch

TEM micrograph of a 4x4 crossbar made of solid-electrolyte switches [src: CDC2009]

Properties:

Switches can be stacked vertically very low resistance in on state (50Ω) Cu based → better compatibility with current CMOS technology than nanowire switches

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 17

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT Thermal Via

CNTs have very high thermal conductance along their axis Use CNT bundles as thermal vias to transfer heat from chip interior to heat sink

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 18

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

A Field Programmable Carbon Nanotube Array (FPCNA)

Designed at University of Illinois at Urbana-Champaign

Recent papers from: Chen, Chilstedt, Dong

Concept and evaluation, no prototype

but: built upon existing base components

2D Design and architecture similar to traditional FPGAs, but uses CNT-based building blocks

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 19

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

CNT-Based LUT

[src: CDC2009]

Lookup Table: fundamental building block in FPGAs Early CNT LUTs: CNT Memory + CMOS MUX Decoder FPCNA LUTs: NRAM + FET Decoder Ribbons of CNTs are used for fault tolerance - CNT fabrication has high defect rates → use several ribbons, chances are some will work

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 20

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

LUT Fabrication Process

Form trench in silicon wafer using standard etching techniques Grow (mostly aligned) CNTs using chemical vapor deposition on separate quartz wafers Transfer continuous CNT array from quartz wafer

• nto substrate using a

stamping technique

Transferring aligned CNT using stamping [src: Kang] Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 21

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

LUT Fabrication Process

Etching of aligned CNT fabric into ribbons [src: CDC2009]

Use etching to partition array into ribbons

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 22

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

LUT Fabrication Process

Burning of metallic CNTs in the LUT decoder region [src: CDC2009]

Burn metallic CNTs from decoder region, but keep them in NRAM region

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 23

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Basic Logic Element (BLE)

In addition to LUT we also need an interface to connect to the rest of the system

Voltage control (set base electrode of CNT NRAM to read, write or erase mode) Address line inversion Registered output (MUX + Flip Flop)

Interface is realized in CMOS BLE = CNT LUT + CMOS Interface

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 24

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Basic Logic Element (BLE)

[src: CDC2009] Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 25

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Configurable Logic Block (CLB)

CLBs = multiple LUTs and their connections (MUX based in CMOS FPGAs)

MUX + NRAM also possible for CNT based FGPAs (but not used for FPCNA)

FPCNA uses solid-electrolyte switch crossbars for routing Output from a BLE can be routed to any other BLE by programming switches

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 26

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Configurable Logic Block (CLB)

[src: CDC2009] Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 27

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

FPCNA Architecture

[src: CDC2009]

Standard island layout consisting of tiles

Tile: 1 Switch Box, 2 Connection Boxes, 1 CLB

CLBs access global routing through Connection Boxes and Switch Box CNT bundles used for interconnects in global routing

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 28

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Routing

[src: CDC2009] left: CMOS switch point, middle: Nanoswitch point with CMOS driving buffers, right: switching examples

In CMOS FPGAs global routing often takes more than half the area Connection Box: FPCNA uses solid-electrolyte switch crossbar Switch Box: consists of switch points.

CMOS: 6 transistors for routing. Also driving buffers, pass transistors FPCNA: Wire segment array, solid-electrolyte switches at

• crosspoints. Keep driving buffers and pass transistors in

CMOS

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 29

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Performance

CNT device variations

CNT type (metallic/semiconducting) not exactly controlled Some CNT transistors may have more semiconducting CNTs in the channel → current variations CNT diameter varies

Performance results based on simulation CNT LUT delay on average 60% of CMOS LUT delay Local CLB interconnect path delay up to 30% of CMOS baseline

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 30

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

3D nFPGA2

University of Illinois (same as FPCNA) Based on 3D nFPGA (2007) concept Design and evaluation, no prototype CMOS Logic, but 3D design with nano-electronic elements

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 31

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Layered Architecture

[src: DCC2009]

1 1

2-layer structure: arrange elements of a tile in a vertical

manner → saves area

Bottom Layer: CMOS Logic Top 1

2-Layer: Nanoswitch Crossbar Layer (solid electrolyte

switches)

Structures can be stacked, connected with “through-silicon vias” (TSVs) CNT bundles used as thermal vias to dissipate heat from inside chip to heat sink

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 32

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Layer Design

Depending on connectivity of local routing, routing can take up a lot of area

e.g. fully connected BLEs (any BLE connected to any other) 65% of area within CLB for local routing in CMOS

3D nFPGA2: local routing with solid-electrolyte switches (as in FPCNA) in addition: routing in crossbar layer (above CMOS layer) to reduce CLB area Global routing

Global CNT interconnect, driving buffers and switch blocks without SRAM cells on CMOS Layer All other routing components in crossbar layer (most connection block components, switch block programmable SRAM cells)

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 33

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Routing Blocks

[src: DCC2009]

Crossbar Layer Tile

CLB routing block, distributed crossbar memory for SRAM in a programmable switch block, 2 connection blocks crossbar built from solid electrolyte switches (high density)

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 34

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Stacking

11

2-layer can be stacked

3D structure allows shorter signal travel times between distant blocks than on 2D layout switch blocks of neighbor slices connected by CNT through-silicon vias

likely better performance than Cu CNT vias also transport heat from inside to heat sink

[src: DCC2009] Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 35

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

Summary

Carbon Nanotubes (CNT) are a candidate for post-silicon technology, many basic electronic components realized FPCNA - 2D FPGA architecture concept using CNT based logic and interconnects using existing components 3D nFPGA2 - 3D FPGA design using stackable layers and CMOS based logic with CNT based routing Challenges

Fault tolerance mandatory with current CNT fabrication techniques Design flow needs to be adjusted

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 36

Carbon Nanotube Based Architectures eFPGAs References CNT FPCNA 3D nFPGA2 Summary

References and Sources

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 37

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

FPGA/ASIC Tradeoffs

Area/Energy Efficiency Flexibility ASIC High Low FPGA Low High eFPGA Medium Medium FPGAs offer a lot of flexibility - which is not always required

when part of an embedded system, the FPGA will usually be used for a certain type of application requirements/constraints known at design time

eFPGAs: trade some of the flexibility of FPGAs for performance/energy efficiency of ASICs

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 38

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

Parametrization of eFPGAs

Cluster - distributed interconnect between LEs instead of central connection box, broadcast lines to share inputs (allow multiple concurrent operations on same data), # LEs in cluster, . . . Logic Element - Connectivity between LEs, register density (1 per LE or less) Configuration Memory - Configuration sharing - several elements configured using same config data Routing Switch - # switch points (reduce amount while sacrificing little performance), switch point connectivity (do we really need 4-way bidirectional routing at every switch point?), # routing tracks (horizontal/vertical) Connection Box - fully connected, unconnected, . . .

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 39

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

commercial eFPGA based products

[src: Stretch] [src: Menta]

2 commercial products using eFPGAs

Stretch S6000 Menta CPUs (e.g. LEON + eFPGA)

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 40

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

ASIP-eFPGA Architecture for Multioperable GNSS Receivers

Receiver for global navigation satellite systems Developed at RWTH Aachen (von Sydow, Blume, Kappen, Noll)

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 41

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

Global Navigation Satellite Systems

Currently: Navstar GPS (USA) In development: Galileo (EU), Compass (China) CDMA baseband processing similar in all systems, but details (e.g. spreading codes) differ Usually in hardware Current example: Glonass (Russia) - not yet CDMA capable - but planed for next satellites in near future Will likely use different spreading codes than established systems ASIP-eFPGA: Use some flexibility in baseband processing to allow for new/upgraded systems, maintain efficiency

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 42

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

ASIP-eFPGA Architecture overview

ASIP handles control flow part arithmetic oriented eFGPA handles data flow part ASIP uses eFPGA via custom instructions Programmer accesses custom instructions via inline assembly

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 43

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

ASIP

Harvard architecture, instruction set based on RISC 5-stage pipeline Custom Instruction format: Source reg, Dest reg, Index Field into Lookup Table LUT entry specifies position and delay of CI implementation on eFPGA

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 44

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

eFPGA

ASIP-eFPGA bit and function slices [src: Neumann]

static reconfiguration

• ptimized for applications using basic arithmetic operators

Tile based layout each cluster tile consists of 16 LEs LEs arranged in

function slices (horizontal) - perform same function on on bit level bit slices (vertical) - all processing elements operate on same bit value

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 45

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

eFPGA

ASIP-eFPGA logic element [src: Sydow]

Logic Elements 3 2-input LUTs 2 XOR gates, MUXes

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 46

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

Interconnect

ASIP-eFPGA cluster [src: Neumann]

island architecture with connection boxes and switches direct neighbors connected to each other Broadcast lines: horizontal broadcasting of operands to

• ther LEs

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 47

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

ASIP-eFPGA communication

[src: Sydow]

tight coupling eFPGA is a reconfigurable functional unit of the ASIP halt signal for ASIP generated automatically if multi-cycle instruction on eFPGA result written from eFPGA to the pipeline register between execute and writeback stage

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 48

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

Design Flow

ASIP specified with “LISA”/“Processor Designer” (CoWare, now part of Synopsys)

cycle accurate model of ASIP generates synthesizable VHDL and coupling control structures for eFPGA (not eFPGA itself), and compiler

eFPGA specified with customizable eFPGA template

hand-optimized layout of Logic Elements, Connection Boxes, Routing Switches placing and routing of eFPGA operators (SI implementations) had to be done manually

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 49

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

Architecture Model

ASIP description in LISA cycle-accurate → VHDL of ASIP/coupling components Manually written behavioral model of eFPGA in VHDL

consists of cycle-accurate descriptions of implemented eFPGA operators

Metrics from standard cell design flow used for physical costs in model Model used for

Design verification of complete architecture Power profile required switching activity of each net/input/output

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 50

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

Results

LT_RISC LT_RISC ASIP-eFPGA ASIP-eFPGA +Mult +Multiplier LP HP LP HP Area [mm2] 0.633 0.655 0.803 0.914 0.829 0.939 Delay [µs] 9191 2545 237 413 184 322 Energy [µJ] 125.8 50.1 4.77 8.12 4.04 7.66

Evaluated using 90nm CMOS process Both High Precision (HP) and Low Precision (LP) signals evaluated LT_RISC is the RISC CPU offered in CoWare’s “Processor Designer” suite. The ASIP used here had some modifications

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 51

Carbon Nanotube Based Architectures eFPGAs References eFPGA Basics ASIP-eFPGA Architecture for Navigation Systems Summary

Summary

ASIP coupled with arithmetic eFPGA as an architecture for a global navigation satellite systems (GNSS) receiver Better area/energy efficiency than GPP , better flexibility than ASIC

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 52

Carbon Nanotube Based Architectures eFPGAs References

Sources and References I

[Ausman] K. Ausman “Introduction to Nanotechnology and its Relevance to IPS” Center for Biological and Environmental Nanotechnology, RICE University [Bondi] Bondi et al. “Laser assisted chemical vapor deposition synthesis of carbon nanotubes and their characterization” Carbon Issue 44, pp. 1393-1403, 2006 [CDC2009] S. Chilstedt, C. Dong, D. Chen “Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture” International Journal

• f Parallel Programming, Vol. 37, Issue 4, pp.

389-416, 2009

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Carbon Nanotube Based Architectures eFPGAs References

Sources and References II

[DCC2009] C. Dong, S. Chilstedt, D. Chen “Reconfigurable Circuit Design with Nanomaterials” Design, Automation & Test in Europe Conference & Exhibition, pp. 442-447, 2009 [HH2009] M. Haselman and S. Hauck “The Future of Integrated Circuits: A Survey of Nanoelectronics” Proceedings of the IEEE, Vol. 98, No. 1, January 2010 [Kaeriyama] Kaeriyama et al. “A Nonvolatile Programmable Solid-Electrolyte Nanometer Switch” IEEE Journal

• f Solid-State Circuits, Vol. 40, No. 1, pp. 168-176

2005

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Carbon Nanotube Based Architectures eFPGAs References

Sources and References III

[Kang] Kang et al. “Printed Multilayer Superstructures of Aligned Single-Walled Carbon Nanotubes for Electronic Applications” NANO LETTERS, Vol. 7,

• No. 11, pp. 3343-3348, 2007

[LBL07] L. Yarris “Falling into the Gap” http://www.lbl.gov/Science-Articles/ Archive/sabl/2007/Nov/gap.html [Maser] Maser et al. “Production of high-density single-walled nanotube material by a simple laser-ablation method” Chemical Physics Letters 292, pp. 587-593, 1998

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Carbon Nanotube Based Architectures eFPGAs References

Sources and References IV

[Menta] Menta S.A.S. “eFPGA Core” http://www.menta.fr/down/ ProductBrief_eFPGA_Core.pdf [Neumann] Neumann et al. “Design flow for embedded FPGAs based on a flexible architecture template” Proceedings of the conference on Design, automation and test in Europe, pp. 56-61, 2008 [Stretch] Stretch Inc. “The S6000 Family of Processors” http://www.stretchinc.com/_files/ s6ArchitectureOverview.pdf

Reconfigurable and Adaptive Systems (RAS) New Directions in FPGA Design 56

Carbon Nanotube Based Architectures eFPGAs References

Sources and References V

[Sydow] von Sydow et al. “ASIP-eFPGA Architecture for Multioperable GNSS Receivers” Lecture Notes in Computer Science, Volume 5114/2008, pp. 136-145, 2008 [Ward] Ward et al., Nantero Inc. “A Non-Volatile Nanoelectromechanical Memory Element Utilizing a Fabric of Carbon Nanotubes” Non-Volatile Memory Technology Symposium, pp. 34-38, 2004 [Zettl] Zettl Research Group “TEM & SEM Images of Nanotubes” http://www.physics.berkeley.edu/ research/zettl/projects/imaging.html

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