❆ ❘❡♣r♦❞✉❝✐❜❧❡ ❘❡s❡❛r❝❤ ▼❡t❤♦❞♦❧♦❣② ❢♦r ❉❡s✐❣♥✐♥❣ ❛♥❞ ❈♦♥❞✉❝t✐♥❣ ❋❛✐t❤❢✉❧ ❙✐♠✉❧❛t✐♦♥s ♦❢ ❉②♥❛♠✐❝ ❚❛s❦✲❜❛s❡❞ ❙❝✐❡♥t✐✜❝ ❆♣♣❧✐❝❛t✐♦♥
▲✉❦❛ ❙t❛♥✐s✐❝
■♥r✐❛✱ ❇♦r❞❡❛✉① ❙✉❞✲❖✉❡st✱ ❋r❛♥❝❡
▼P❈❉❋ s❡♠✐♥❛r
- ❛r❝❤✐♥❣
r sr t - - PowerPoint PPT Presentation
r sr t r s t t ts
■♥r✐❛✱ ❇♦r❞❡❛✉① ❙✉❞✲❖✉❡st✱ ❋r❛♥❝❡
Bachelor (CS specialty) EE faculty Belgrade, Serbia Phd (supervisors A. Legrand & J.F . Mehaut) Grenoble, France Modeling and simulation of dynamic task-based applications Methodology for reproducible research Statistical analysis, trace visualizations Research Master (parallelism specialty) Grenoble, France Benchmarking CPU cache modeling ARM vs Intel 2011 2012 2013 2014 2015 2017 2016 PostDoc Bordeaux, France Performance optimization Large scale simulations Modeling complex kernels Simulating openQCD
✷ ✴ ✷✾
Bachelor (CS specialty) EE faculty Belgrade, Serbia Phd (supervisors A. Legrand & J.F . Mehaut) Grenoble, France Modeling and simulation of dynamic task-based applications Methodology for reproducible research Statistical analysis, trace visualizations Research Master (parallelism specialty) Grenoble, France Benchmarking CPU cache modeling ARM vs Intel 2011 2012 2013 2014 2015 2017 2016 PostDoc Bordeaux, France Performance optimization Large scale simulations Modeling complex kernels Simulating openQCD
✷ ✴ ✷✾
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✹ ✴ ✷✾
✹ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
✺ ✴ ✷✾
POTRF (RW,A[j][j]);
TRSM (RW,A[i][j], R,A[j][j]);
SYRK (RW,A[i][i], R,A[i][j]);
GEMM (RW,A[i][k],
GEMM SYRK TRSM POTRF
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Performance Profile
✾ ✴ ✷✾
Performance Profile
✾ ✴ ✷✾
✶✵ ✴ ✷✾
... #ifdef STARPU_SIMGRID MSG_process_sleep((float) dim * alloc_cost_per_byte); #else if (_starpu_can_submit_cuda_task()) { cudaError_t cures; cures = cudaHostAlloc(A, dim, cudaHostAllocPortable); ...
✶✶ ✴ ✷✾
✶✷ ✴ ✷✾
GPU7 GPU6 GPU2 GPU3 CPU GPU4 GPU1 GPU0 GPU5
✶✷ ✴ ✷✾
GEMM SYRK TRSM POTRF
✶✸ ✴ ✷✾
Hannibal: 3 QuadroFX5800 Attila: 3 TeslaC2050 Mirage: 3 TeslaM2070 Conan: 3 TeslaM2075 1000 2000 3000 4000 1000 2000 3000 4000 Cholesky LU 20K 40K 60K 80K 20K 40K 60K 80K 20K 40K 60K 80K 20K 40K 60K 80K
Matrix dimension GFlop/s
Frogkepler: 2 K20 Pilipili2: 2 K40 Idgraf: 8 TeslaC2050 1000 2000 3000 4000 1000 2000 3000 4000 Cholesky LU 20K 40K 60K 80K 20K 40K 60K 80K 20K 40K 60K 80K
Matrix dimension GFlop/s Experiment Type
Native SimGrid
❬✶❪ ▲✳ ❙t❛♥✐s✐❝✱ ❙✳ ❚❤✐❜❛✉❧t✱ ❆✳ ▲❡❣r❛♥❞✱ ❇✳ ❱✐❞❡❛✉✱ ❛♥❞ ❏✳✲❋✳ ▼é❤❛✉t✳ ❋❛✐t❤❢✉❧ P❡r❢♦r♠❛♥❝❡ Pr❡❞✐❝t✐♦♥ ♦❢ ❛ ❉②♥❛♠✐❝ ❚❛s❦✲❇❛s❡❞ ❘✉♥t✐♠❡ ❙②st❡♠ ❢♦r ❍❡t❡r♦❣❡♥❡♦✉s ▼✉❧t✐✲❈♦r❡ ❆r❝❤✐t❡❝t✉r❡s✳ ❈♦♥❝✉rr❡♥❝② ❛♥❞ ❈♦♠♣✉t❛t✐♦♥✿ Pr❛❝t✐❝❡ ❛♥❞ ❊①♣❡r✐❡♥❝❡✱ ♣❛❣❡ ✶✻✱ ▼❛② ✷✵✶✺✳ ❬✷❪ ▲✳ ❙t❛♥✐s✐❝✱ ❙✳ ❚❤✐❜❛✉❧t✱ ❆✳ ▲❡❣r❛♥❞✱ ❇✳ ❱✐❞❡❛✉✱ ❛♥❞ ❏✳✲❋✳ ▼é❤❛✉t✳ ▼♦❞❡❧✐♥❣ ❛♥❞ ❙✐♠✉❧❛t✐♦♥ ♦❢ ❛ ❉②♥❛♠✐❝ ❚❛s❦✲❇❛s❡❞ ❘✉♥t✐♠❡ ❙②st❡♠ ❢♦r ❍❡t❡r♦❣❡♥❡♦✉s ▼✉❧t✐✲❝♦r❡ ❆r❝❤✐t❡❝t✉r❡s✳ ■♥ ❊✉r♦✲♣❛r ✲ ✷✵t❤ ■♥t❡r♥❛t✐♦♥❛❧ ❈♦♥❢❡r❡♥❝❡ ♦♥ P❛r❛❧❧❡❧ Pr♦❝❡ss✐♥❣✱ ❊✉r♦✲P❛r ✷✵✶✹✱ ▲◆❈❙ ✽✻✸✷✱ ♣❛❣❡s ✺✵✕✻✷✱ P♦rt♦✱ P♦rt✉❣❛❧✱ ❆✉❣✳ ✷✵✶✹✳ ✶✹ ✴ ✷✾
❬✶❪ ▲✳ ❙t❛♥✐s✐❝✱ ❙✳ ❚❤✐❜❛✉❧t✱ ❆✳ ▲❡❣r❛♥❞✱ ❇✳ ❱✐❞❡❛✉✱ ❛♥❞ ❏✳✲❋✳ ▼é❤❛✉t✳ ❋❛✐t❤❢✉❧ P❡r❢♦r♠❛♥❝❡ Pr❡❞✐❝t✐♦♥ ♦❢ ❛ ❉②♥❛♠✐❝ ❚❛s❦✲❇❛s❡❞ ❘✉♥t✐♠❡ ❙②st❡♠ ❢♦r ❍❡t❡r♦❣❡♥❡♦✉s ▼✉❧t✐✲❈♦r❡ ❆r❝❤✐t❡❝t✉r❡s✳ ❈♦♥❝✉rr❡♥❝② ❛♥❞ ❈♦♠♣✉t❛t✐♦♥✿ Pr❛❝t✐❝❡ ❛♥❞ ❊①♣❡r✐❡♥❝❡✱ ♣❛❣❡ ✶✻✱ ▼❛② ✷✵✶✺✳ ❬✷❪ ▲✳ ❙t❛♥✐s✐❝✱ ❙✳ ❚❤✐❜❛✉❧t✱ ❆✳ ▲❡❣r❛♥❞✱ ❇✳ ❱✐❞❡❛✉✱ ❛♥❞ ❏✳✲❋✳ ▼é❤❛✉t✳ ▼♦❞❡❧✐♥❣ ❛♥❞ ❙✐♠✉❧❛t✐♦♥ ♦❢ ❛ ❉②♥❛♠✐❝ ❚❛s❦✲❇❛s❡❞ ❘✉♥t✐♠❡ ❙②st❡♠ ❢♦r ❍❡t❡r♦❣❡♥❡♦✉s ▼✉❧t✐✲❝♦r❡ ❆r❝❤✐t❡❝t✉r❡s✳ ■♥ ❊✉r♦✲♣❛r ✲ ✷✵t❤ ■♥t❡r♥❛t✐♦♥❛❧ ❈♦♥❢❡r❡♥❝❡ ♦♥ P❛r❛❧❧❡❧ Pr♦❝❡ss✐♥❣✱ ❊✉r♦✲P❛r ✷✵✶✹✱ ▲◆❈❙ ✽✻✸✷✱ ♣❛❣❡s ✺✵✕✻✷✱ P♦rt♦✱ P♦rt✉❣❛❧✱ ❆✉❣✳ ✷✵✶✹✳ ✶✹ ✴ ✷✾
✶
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✸
Native, Do_subtree 2 4 6 50 100
Number of Occurances
Native, Activate 5 10 15 20 250 500 750 Native, Panel 50 100 150 200 25 50 75 100 Native, Update 2000 4000 20 40 60 Native, Assemble 50 100 150 200 250 10 20 30 Native, Deactivate 10 20 25 50 75 Kernel Do_subtree Activate Panel Update Assemble Deactivate
✶✺ ✴ ✷✾
Native, Do_subtree SimGrid, Do_subtree 3 6 9 3 6 9 50 100
Number of Occurances
Native, Activate SimGrid, Activate 5 10 15 20 5 10 15 20 250 500 750 Native, Panel SimGrid, Panel 100 200 100 200 25 50 75 Native, Update SimGrid, Update 2000 4000 6000 2000 4000 6000 20 40 60 Native, Assemble SimGrid, Assemble 100 200 300 100 200 300 10 20 30 Native, Deactivate SimGrid, Deactivate 10 20 30 10 20 30 25 50 75 Kernel Do_subtree Activate Panel Update Assemble Deactivate
✶✻ ✴ ✷✾
10 20 30 40 50 200 400 t p − 6 k a r t e d E t e r n i t y I I _ E d e g m e h i r l a m e 1 8 T F 1 6 R u c c i 1 s l s T F 1 7
Duration [s] Experiment Type
Native SimGrid
qr_mumps
100 200 300 2M 4M 8M 16M 32M 64M
Number of Particles Duration [s] Experiment Type
Native SimGrid
ScalFMM
❬✸❪ ▲✳ ❙t❛♥✐s✐❝✱ ❊✳ ❆❣✉❧❧♦✱ ❆✳ ❇✉tt❛r✐✱ ❆✳ ●✉❡r♠♦✉❝❤❡✱ ❆✳ ▲❡❣r❛♥❞✱ ❋✳ ▲♦♣❡③✱ ❛♥❞ ❇✳ ❱✐❞❡❛✉✳ ❋❛st ❛♥❞ ❆❝❝✉r❛t❡ ❙✐♠✉❧❛t✐♦♥ ♦❢ ▼✉❧t✐t❤r❡❛❞❡❞ ❙♣❛rs❡ ▲✐♥❡❛r ❆❧❣❡❜r❛ ❙♦❧✈❡rs✳ P❛r❛❧❧❡❧ ❛♥❞ ❉✐str✐❜✉t❡❞ ❙②st❡♠s ✭■❈P❆❉❙✮✱ ❉❡❝✳ ✷✵✶✺✳ ❬✹❪ ❊✳ ❆❣✉❧❧♦✱ ❇✳ ❇r❛♠❛s✱ ❖✳ ❈♦✉❧❛✉❞✱ ▲✳ ❙t❛♥✐s✐❝✱ ❛♥❞ ❙✳ ❚❤✐❜❛✉❧t✳ ▼♦❞❡❧✐♥❣ ■rr❡❣✉❧❛r ❑❡r♥❡❧s ♦❢ ❚❛s❦✲❜❛s❡❞ ❝♦❞❡s✿ ■❧❧✉str❛t✐♦♥ ✇✐t❤ t❤❡ ❋❛st ▼✉❧t✐♣♦❧❡ ▼❡t❤♦❞✳ s✉❜♠✐tt❡❞ t♦ ❚r❛♥s❛❝t✐♦♥ ♦♥ ▼❛t❤❡♠❛t✐❝❛❧ ❙♦❢t✇❛r❡ ✭❚❖▼❙✮✱ ❬❘❡s❡❛r❝❤ ❘❡♣♦rt❪ ✾✵✸✻✱ ■◆❘■❆ ❇♦r❞❡❛✉①✳ ♣♣✳✸✺✳ ❋❡❜✳ ✷✵✶✼✳ ✶✼ ✴ ✷✾
✶
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DMDA DMDAR DMDAS 500 1000 1500 20K 40K 60K 80K 20K 40K 60K 80K 20K 40K 60K 80K
Matrix dimension GFlop/s Experiment Type
Native SimGrid ✶✽ ✴ ✷✾
Experiment number 1 Experiment number 2 Experiment number 3 Experiment number 4 1 2 3 1 2 3 1 2 3 1 2 3 10,000 20,000 30,000 40,000
Time [ms] Allocated Memory [GiB] ✶✾ ✴ ✷✾
Native 1 Native 2 SimGrid Native 3 1 2 3 1 2 3 1 2 3 1 2 3 10,000 20,000 30,000 40,000
Time [ms] Allocated Memory [GiB] ✶✾ ✴ ✷✾
30 60 90 4 10 20 40 100 400
Number of Threads Duration [s] Experiment Type
Native SimGrid
✷✵ ✴ ✷✾
✶
✷
✸
✷✶ ✴ ✷✾
✶
✷
✸
✷✷ ✴ ✷✾
❊①♣❡r✐♠❡♥t ❈♦❞❡ ✭✇♦r❦❧♦❛❞ ✐♥❥❡❝t♦r✱ ❱▼ r❡❝✐♣❡s✱ ✳✳✳✮ Pr♦❝❡ss✐♥❣ ❈♦❞❡ ❆♥❛❧②s✐s ❈♦❞❡ Pr❡s❡♥t❛t✐♦♥ ❈♦❞❡ ❆♥❛❧②t✐❝ ❉❛t❛ ❈♦♠♣✉t❛t✐♦♥❛❧ ❘❡s✉❧ts ▼❡❛s✉r❡❞ ❉❛t❛ ◆✉♠❡r✐❝❛❧ ❙✉♠♠❛r✐❡s ❋✐❣✉r❡s ❚❛❜❧❡s ❚❡①t
✭❉❡s✐❣♥ ♦❢ ❊①♣❡r✐♠❡♥ts✮ Pr♦t♦❝♦❧ ❙❝✐❡♥t✐✜❝ ◗✉❡st✐♦♥ P✉❜❧✐s❤❡❞ ❆rt✐❝❧❡ ◆❛t✉r❡✴❙②st❡♠✴✳✳✳
■♥s♣✐r❡❞ ❜② ❘♦❣❡r ❉✳ P❡♥❣✬s ❧❡❝t✉r❡ ♦♥ r❡♣r♦❞✉❝✐❜❧❡ r❡s❡❛r❝❤✱ ▼❛② ✷✵✶✹
✷✸ ✴ ✷✾
❊①♣❡r✐♠❡♥t ❈♦❞❡ ✭✇♦r❦❧♦❛❞ ✐♥❥❡❝t♦r✱ ❱▼ r❡❝✐♣❡s✱ ✳✳✳✮ Pr♦❝❡ss✐♥❣ ❈♦❞❡ ❆♥❛❧②s✐s ❈♦❞❡ Pr❡s❡♥t❛t✐♦♥ ❈♦❞❡ ❆♥❛❧②t✐❝ ❉❛t❛ ❈♦♠♣✉t❛t✐♦♥❛❧ ❘❡s✉❧ts ▼❡❛s✉r❡❞ ❉❛t❛ ◆✉♠❡r✐❝❛❧ ❙✉♠♠❛r✐❡s ❋✐❣✉r❡s ❚❛❜❧❡s ❚❡①t
✭❉❡s✐❣♥ ♦❢ ❊①♣❡r✐♠❡♥ts✮ Pr♦t♦❝♦❧ ❙❝✐❡♥t✐✜❝ ◗✉❡st✐♦♥ P✉❜❧✐s❤❡❞ ❆rt✐❝❧❡ ◆❛t✉r❡✴❙②st❡♠✴✳✳✳
✷✸ ✴ ✷✾
Time Experiment plan Memory allocation Operating system Sequence order Repetitions Element type Allocation technique Scheduling priority CPU frequency Core pinning Dedication Optimization Loop unrolling Intel ARM Cycles Size Stride Architecture Compilation Kernel Bandwidth
❬✺❪ ▲✳ ❙t❛♥✐s✐❝✱ ▲✳ ▼✳ ❙❝❤♥♦rr✱ ❆✳ ❉❡❣♦♠♠❡✱ ❋✳ ❍❡✐♥r✐❝❤✱ ❆✳ ▲❡❣r❛♥❞✱ ❛♥❞ ❇✳ ❱✐❞❡❛✉✳ ❈❤❛r❛❝t❡r✐③✐♥❣ t❤❡ P❡r❢♦r♠❛♥❝❡ ♦❢ ▼♦❞❡r♥ ❆r❝❤✐t❡❝t✉r❡s ❚❤r♦✉❣❤ ❖♣❛q✉❡ ❇❡♥❝❤♠❛r❦s✿ P✐t❢❛❧❧s ▲❡❛r♥❡❞ t❤❡ ❍❛r❞ ❲❛②✳ s✉❜♠✐tt❡❞ t♦ ■♥t❡r♥❛t✐♦♥❛❧ ❲♦r❦s❤♦♣ ♦♥ ❘❡♣r♦❞✉❝✐❜✐❧✐t② ✐♥ P❛r❛❧❧❡❧ ❈♦♠♣✉t✐♥❣ ✭❘❊PP❆❘✮✱ ✷✵✶✼✳ ✷✹ ✴ ✷✾
730 CPE 368 ABE 434 CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 CPU12 CPU13 CPU14 CPU15 CPU16 CPU17 CPU18 CPU19 CPU20 CPU21 CPU22 CPU23 CPU24 CUDA0 CUDA1 CUDA2 200 400 600 Time [ms] Resources dgemm dpotrf dsyrk dtrsm Idle/Sleeping Critical Paths 1 2
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 CPU12 CPU13 CPU14 CPU15 CPU16 CPU17 CPU18 CPU19 CPU20 CPU21 CPU22 CPU23 CPU24 CUDA0 CUDA1 CUDA2 Resources 20 40 60 k iteration 5000 10000 15000 20000 # tasks 66965 CPE 2201 ABE 59748 0.7% 0.9% 1.0% 0.9% 0.9% 1.0% 1.0% 0.8% 1.0% 1.0% 1.0% 0.9% 0.9% 1.0% 1.3% 1.3% 1.2% 1.3% 1.4% 1.4% 1.6% 1.5% 1.6% 1.4% 1.6% 20.6% 20.2% 19.9% 62725 CPE 2149 ABE 59464 0.4% 0.6% 0.6% 0.7% 0.9% 1.0% 1.0% 0.9% 1.0% 1.0% 1.0% 0.9% 0.9% 0.9% 1.0% 1.0% 1.0% 0.9% 1.0% 1.1% 1.0% 1.1% 1.0% 1.0% 1.0% 5.9% 1.9% 2.0% 60987 CPE 2146 ABE 58452 1.1% 1.3% 1.2% 1.3% 1.3% 1.5% 1.4% 1.4% 1.5% 1.5% 1.3% 1.4% 1.2% 1.3% 1.5% 1.5% 1.5% 1.5% 1.4% 1.5% 1.5% 1.5% 1.4% 1.4% 1.5% 4.0% 2.2% 2.2% 20 40 60 500 1000 1500 500 1000 1500 5000 10000 15000 20000 20 40 60 500 1000 1500 500 1000 1500 5000 10000 15000 20000 20 40 60 500 1000 1500 500 1000 1500 20000 40000 60000 20000 40000 60000 20000 40000 60000 dgemm dpotrf dsyrk dtrsm Idle/Sleeping 20000 40000 60000 20000 40000 60000 20000 40000 60000 Time [ms] CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA 64061 CPE 2114 ABE 60004 12.5% 12.8% 12.3% 11.6% 13.5% 13.6% 14.6% 14.3% 12.0% 11.6% 11.2% 3.2% 2.7% 3.1% 3.7% 3.8% 3.1% 2.6% 3.7% 4.0% 4.1% 3.7% 2.9% 3.9% 3.0% 3.6% 2.2% 2.6% 60174 CPE 2159 ABE 59017 1.0% 0.8% 1.1% 1.3% 1.3% 1.5% 1.5% 1.7% 1.7% 1.8% 1.8% 1.8% 1.9% 2.0% 2.0% 2.1% 2.3% 2.3% 2.3% 2.2% 2.3% 2.3% 2.5% 2.5% 2.4% 2.5% 1.1% 0.9% 59577 CPE 2160 ABE 57603 0.9% 1.3% 0.9% 1.0% 1.0% 0.9% 1.0% 1.1% 0.9% 0.9% 1.0% 1.0% 0.9% 1.1% 1.1% 1.0% 1.2% 1.0% 1.2% 1.0% 1.1% 1.1% 1.2% 0.9% 0.9% 3.2% 1.4% 1.4% CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 CPU12 CPU13 CPU14 CPU15 CPU16 CPU17 CPU18 CPU19 CPU20 CPU21 CPU22 CPU23 CPU24 CUDA0 CUDA1 CUDA2 20 40 60 20000 40000 60000 20000 40000 60000 20000 40000 60000 20000 40000 60000 20000 40000 60000 20000 40000 60000 Time [ms] Resources k iteration dgemm dpotrf dsyrk dtrsm Idle/Sleeping 5000 10000 15000 20000 20 40 60 500 1000 1500 500 1000 1500 5000 10000 15000 20000 20 40 60 500 1000 1500 500 1000 1500 5000 10000 15000 20000 20 40 60 500 1000 1500 500 1000 1500 CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA CPU CUDA # tasks❬✻❪ ❱✳ ●✳ P✐♥t♦✱ ▲✳ ❙t❛♥✐s✐❝✱ ❆✳ ▲❡❣r❛♥❞✱ ▲✳ ▼✳ ❙❝❤♥♦rr✱ ❛♥❞ ❙✳ ❚❤✐❜❛✉❧t✳ ❆♥❛❧②③✐♥❣ ❉②♥❛♠✐❝ ❚❛s❦✲❇❛s❡❞ ❆♣♣❧✐❝❛t✐♦♥s ♦♥ ❍②❜r✐❞ P❧❛t❢♦r♠s✿ ❆♥ ❆❣✐❧❡ ❙❝r✐♣t✐♥❣ ❆♣♣r♦❛❝❤✳ ✸r❞ ❲♦r❦s❤♦♣ ♦♥ ❱✐s✉❛❧ P❡r❢♦r♠❛♥❝❡ ❆♥❛❧②s✐s ✭❱P❆✮✱ ◆♦✈ ✷✵✶✻✱ ❙❛❧t ▲❛❦❡ ❈✐t②✱ ❯♥✐t❡❞ ❙t❛t❡s ✷✺ ✴ ✷✾
src
data art/art1 xp/foo1 xp/foo2
❬✼❪ ▲✳ ❙t❛♥✐s✐❝✱ ❆✳ ▲❡❣r❛♥❞✱ ❛♥❞ ❱✳ ❉❛♥❥❡❛♥✳ ❆♥ ❊✛❡❝t✐✈❡ ●✐t ❆♥❞ ❖r❣✲▼♦❞❡ ❇❛s❡❞ ❲♦r❦✢♦✇ ❋♦r ❘❡♣r♦❞✉❝✐❜❧❡ ❘❡s❡❛r❝❤✳ ❆❈▼ ❙■●❖P❙ ❖♣❡r❛t✐♥❣ ❙②st❡♠s ❘❡✈✐❡✇✱ ✹✾✿✻✶ ✕ ✼✵✱ ✷✵✶✺✳ ❙♣❡❝✐❛❧ ❚♦♣✐❝✿ ❘❡♣❡❛t❛❜✐❧✐t② ❛♥❞ ❙❤❛r✐♥❣ ♦❢ ❊①♣❡r✐♠❡♥t❛❧ ❆rt✐❢❛❝ts✳ ❬✽❪ ▲✳ ❙t❛♥✐s✐❝ ❛♥❞ ❆✳ ▲❡❣r❛♥❞✳ ❊✛❡❝t✐✈❡ ❘❡♣r♦❞✉❝✐❜❧❡ ❘❡s❡❛r❝❤ ✇✐t❤ ❖r❣✲▼♦❞❡ ❛♥❞ ●✐t✳ ■♥ ✶st ■♥t❡r♥❛t✐♦♥❛❧ ❲♦r❦s❤♦♣ ♦♥ ❘❡♣r♦❞✉❝✐❜✐❧✐t② ✐♥ P❛r❛❧❧❡❧ ❈♦♠♣✉t✐♥❣✱ P♦rt♦✱ P♦rt✉❣❛❧✱ ❆✉❣✳ ✷✵✶✹✳ ✷✻ ✴ ✷✾
✷✼ ✴ ✷✾
✶
✷
✸
✷✽ ✴ ✷✾
Regular algorithms Dynamic task-based HPC applications Research methodology Benchmarks Basic modeling 2013 2014 2015 2016 2017 2019 2018 Numerical (irregular) libraries Performance optimization Large scale executions Real-life applications Collaboration with other domain experts
✷✾ ✴ ✷✾
Regular algorithms Dynamic task-based HPC applications Research methodology Benchmarks Basic modeling 2013 2014 2015 2016 2017 2019 2018 Numerical (irregular) libraries Performance optimization Large scale executions Real-life applications Collaboration with other domain experts
✷✾ ✴ ✷✾