Quo Vad adis? = = Wher ere e are e you going? 2 I I I -V - - PowerPoint PPT Presentation

I I I -V CMOS: Quo Vad

adis?

• J. A. del Alamo, X. Cai, W. Lu, A. Vardi, and X. Zhao

Microsystems Technology Laboratories

Massachusetts Institute of Technology

Compound Semiconductor Week 2018 Cambridge, MA, May 29-June 1, 2018 Acknowledgements:

• Former students and collaborators: D. Antoniadis, E. Fitzgerald, J. Grajal, J. Lin
• Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman,

NSF, Samsung, SRC

• Labs at MIT: MTL, EBL

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Quo Vad adis? = = Wher ere e are e you going?

I I I -V CMOS: The Promise

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Scaling: Voltage ↓  Current density ↓  Performance ↓

del Alamo, Nature 2011

Current density of n-MOSFETs at nominal voltage: Source injection velocity: Si vs. InGaAs FETs

vinj(InGaAs) > 2vinj(Si) at less than half VDD  high current at low voltage

n-MOSFETs in Intel’s nodes at nominal voltage

Transconductance of Planar Si vs. I nGaAs MOSFETs

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“Comparisons always fraught with danger…”

n-MOSFETs in Intel’s nodes at nominal voltage

Transconductance of Planar Si vs. I nGaAs MOSFETs

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“Comparisons always fraught with danger…”

• InGaAs stagnant for a long time

n-MOSFETs in Intel’s nodes at nominal voltage

Transconductance of Planar Si vs. I nGaAs MOSFETs

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“Comparisons always fraught with danger…”

• Rapid recent progress
• InGaAs exceeds Si

n-MOSFETs in Intel’s nodes at nominal voltage

Transconductance of Planar Si vs. I nGaAs MOSFETs

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“Comparisons always fraught with danger…”

• Rapid recent progress
• InGaAs exceeds Si

MIT (VDS=0.5 V)

Lin, IEDM 2014 EDL 2016

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Many requirements for a successful logic technology

• 1. ON current
• 2. OFF current
• 3. Scalability
• 4. Stability
• 5. Manufacturing robustness
• 6. Si integration

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Evolution of transistor structure for improved scalability

Planar bulk MOSFET Thin-body SOI MOSFET Nanowire MOSFET

Enhanced gate control  improved scalability

FinFET

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Evolution of transistor structure for improved scalability

Enhanced gate control  improved scalability

FinFET

Transconductance of planar Si vs. I nGaAs MOSFETs

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Transconductance of Si vs. I nGaAs FinFETs

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Transconductance of Si vs. I nGaAs FinFETs

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gm normalized by fin width

Wf FinFET: large increase in current density per unit footprint over planar MOSFET

Transconductance of Si vs. I nGaAs FinFETs

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Best InGaAs FinFETs nearly match 14 nm Si MOSFETs

MIT (VDS=0.5 V)

gm normalized by fin width

Wf

Transconductance of Si vs. I nGaAs FinFETs

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10 nm node Si MOSFETs a great new challenge!

10 nm node Intel (VDS=0.7 V)

gm normalized by fin width

Wf

I nGaAs FinFETs @ MI T

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Vardi, DRC 2014, EDL 2015, IEDM 2015

Key enabling technologies: BCl3/SiCl4/Ar RIE + digital etch

• Sub-10 nm fin width
• Aspect ratio > 20
• Vertical sidewalls

I nGaAs FinFETs @ MI T

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Vardi, IEDM 2017

• Si-compatible process
• Contact-first, gate-last process
• Fin etch mask left in place  double-gate MOSFET

InAlAs InGaAs

n+-InGaAs

W/Mo Lg SiO2 HSQ High-K InP δ - Si InP Mo Mo HSQ High-K InGaAs

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Most aggressively scaled FinFET

Wf=5 nm, Lg=50 nm, Hc=50 nm (AR=10), EOT=0.8 nm: Vardi, IEDM 2017 At VDS=0.5 V:

• gm=565 µS/µm
• Ron=660 Ω.µm
• Ssat=75 mV/dec
• DIBL=22 mV/V
• 0.2

0.0 0.2 0.4 0.6 0.8 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3

Ssat=75 mV/dec Slin=65 mV/dec

50 mV VDS=500 mV Id [A/µm] VGS [V] Lg=50 nm Wf=5 nm

• 0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

100 200 300 400 500 600 700 gm [µS/µm] VGS [V] VDS=0.5 V Lg=50 nm Wf=5 nm

0.0 0.1 0.2 0.3 0.4 0.5 50 100 150 Id [µA/µm] VGS [V]

VGS=-0.2 to 0.5 V ∆VGS=0.1 V

gm,max=565 µS/µm

Normalized by conducting gate periphery = 2Hc

5 10 15 20 25 200 400 600 800 1000 Ron[Ω-µm] Wf [nm]

5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 gm[mS/µm] Wf [nm]

Fin-width scaling of ON-state current

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• gm independent of Wf down

to Wf=7 nm

• In planar MOSFET (x=0.53)

expect gm~ 2.2 mS/µm

• Missing performance hints

at sidewall damage

Vardi, IEDM 2017 in planar MOSFETs expect 2.2 mS/µm

Lg=40-60 nm VDS = 0.5 V Normalized by conducting gate periphery = 2Hc

5 10 15 20 25 40 60 80 100 120 Ssat Slin S [mV/dec] Wf [nm]

Fin-width scaling of OFF-state current

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• Excellent subthreshold swing scaling behavior
• From long Lg devices: Dit ~ 8x1011 cm-2.eV-1

Vardi, IEDM 2017

Slin (VDS = 50 mV) Ssat (VDS = 0.5 V) Lg=40-60 nm

• 0.2

0.0 0.2 0.4 0.6 0.8 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3

Ssat=75 mV/dec Slin=65 mV/dec

50 mV VDS=500 mV Id [A/µm] VGS [V] Lg=50 nm Wf=5 nm

Excess OFF-state current

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Band-to-band tunneling (BTBT) at drain end of channel Classic BTBT behavior in long-channel devices

Zhao, EDL 2018

Excess OFF-state current

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• Large BJT current gain (up to ~100)
• Short Lg: β ~ 1/Lg
• Long Lg: β ~ exp(-Lg/Ld), Ld ≈ 2-4 µm

Zhao, EDL 2018, CSW 2018

Current multiplication through parasitic bipolar transistor

• 1 slope

Manufacturing robustness: impact of fin width on VT

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• Strong VT sensitivity for Wf < 10 nm; much worse than Si
• Due to quantum effects
• Big concern for future manufacturing

InGaAs doped-channel FinFETs: 50 nm thick, ND~1018 cm-3

Vardi, IEDM 2015

T=90K

• ∆Vt: power law in time and stress voltage
• Typical of PBTI (Positive Bias Stress

Instability)

MOSFET threshold voltage stability

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Planar InGaAs MOSFETs under forward-gate stress (Vgs>0):

Cai, IEDM 2016 2.5 nm HfO2

• ∆gm,max and ∆Vt,lin correlated
• Negligible change in S
• 30 mV shift in 10 years for Vgt= 0.4 V
• Oxide traps = O vacancies in HfO2

MOSFET stability due to oxide traps

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Planar InGaAs MOSFETs under forward-gate stress:

Excellent review by Franco, IEDM 2017

0.4 0.6 0.8 1 1.2 10

1

10

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10

5

10

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10

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time to 30mV shift (s) Vgt,stress (V)

Vgt=0.4 V @ 10 years

Cai, IEDM 2016

Other manifestations of oxide traps

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Cai, CSW 2018 C-V frequency dispersion gm frequency dispersion Pulsed vs. DC

Also: Cartier, ESSDERC 2017

• Frequency dispersion in Cg and gm
• Pulsed I-V ≠ DC I-V
• DC underestimates transistor potential

Also: Johansson, ESSDERC 2013

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I nGaAs Vertical Nanowire MOSFETs

VNW MOSFET

Vertical NW MOSFET:  uncouples footprint scaling from Lg, Lspacer, and Lc scaling

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I nGaAs VNW-MOSFETs by top-down approach @ MI T

• Top-down approach: flexible and manufacturable
• Critical technologies: precision RIE + alcohol-based digital etch

Lu, EDL 2017

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D= 7 nm I nGaAs VNW MOSFET

Single nanowire MOSFET:

• Lch= 80 nm
• 2.5 nm Al2O3 (EOT = 1.3 nm)
• gm,pk=1700 µS/µm
• Top contact = key problem

Zhao, IEDM 2017

• 0.2

0.0 0.2 0.4 0.6 10

• 9

10

• 8

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• 7

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• 6

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• 5

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• 4

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• 3

D = 7 nm

Slin/Ssat = 85/90 mV/dec DIBL = 222 mV/dec Vds=0.5 V Vgs(V) Id (A/µm) Vds=0.05 V

0.0 0.1 0.2 0.3 0.4 0.5 100 200 300 400 500 600 700 800 Id (µA/µm)

Vgs= 0 V to 0.8 V in 0.1 V step D = 7 nm Top contact = Drain

Vds (V) 0.0 0.1 0.2 0.3 0.4 0.5 20 40 60 80 100 Vgs= 0 V to 0.8 V in 0.1 V step

D = 7 nm Top contact = Source Vds (V)

Id (µA/µm)

Benchmark with Si/ Ge VNW MOSFETs

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• First sub-10 nm diameter VNW FET of any kind on any material system
• InGaAs competitive with Si [hard to add strain]

Peak gm of InGaAs (VDS=0.5 V), Si and Ge VNW MOSFETs

MIT @ VDS=0.5 V

Zhao, IEDM 2017

I nGaAs Vertical Nanowires on Si by direct growth

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Selective-Area Epitaxy (SAE) Au seed Vapor-Solid-Liquid (VLS) Technique InAs NWs on Si by SAE Riel, MRS Bull 2014 Riel, IEDM 2012

VNW MOSFETs: path for III-V integration

• n Si for future CMOS

Conclusions

1. Great recent progress on planar, fin and nanowire InGaAs MOSFETs 2. Device performance still lacking for 3D architecture designs

 severe oxide trapping masks true transistor potential

3. Serious challenges identified: excess off-current, stability, manufacturability, integration with Si 4. Vertical Nanowire MOSFET: ultimate scalable transistor; integrates well on Si

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