Provably Secure Higher-Order Masking of AES Matthieu Rivain - - PowerPoint PPT Presentation

provably secure higher order masking of aes
SMART_READER_LITE
LIVE PREVIEW

Provably Secure Higher-Order Masking of AES Matthieu Rivain - - PowerPoint PPT Presentation

Provably Secure Higher-Order Masking of AES Matthieu Rivain Emmanuel Prouff CryptoExperts Oberthur CHES 2010, Santa Barbara, Aug. 20 th CHES 2010 Provably Secure Higher-Order Masking of AES Outline 1 Introduction Higher-Order


slide-1
SLIDE 1

Provably Secure Higher-Order Masking of AES

Matthieu Rivain Emmanuel Prouff CryptoExperts Oberthur

CHES 2010, Santa Barbara, Aug. 20th

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-2
SLIDE 2

Outline 1 Introduction

Higher-Order Masking ISW Scheme (CRYPTO’03)

2 Our Scheme

Masking the S-box Masking the Whole AES Security Implementation Results

3 Conclusion

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-3
SLIDE 3

Outline 1 Introduction

Higher-Order Masking ISW Scheme (CRYPTO’03)

2 Our Scheme

Masking the S-box Masking the Whole AES Security Implementation Results

3 Conclusion

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-4
SLIDE 4

Higher-Order Masking

Basic principle

Every key-dependent variable x is shared into d + 1 variables

⊥ x0 ⊥ x1 ⊥ · · · ⊥ xd = x ⊥

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-5
SLIDE 5

Higher-Order Masking

Basic principle

Every key-dependent variable x is shared into d + 1 variables

⊥ x0 ⊕ x1 ⊕ · · · ⊕ xd = x ⊥

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-6
SLIDE 6

Higher-Order Masking

Basic principle

Every key-dependent variable x is shared into d + 1 variables

⊥ x0 ⊕ x1 ⊕ · · · ⊕ xd = x ⊥

The masks (i ≥ 1): xi ← $

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-7
SLIDE 7

Higher-Order Masking

Basic principle

Every key-dependent variable x is shared into d + 1 variables

⊥ x0 ⊕ x1 ⊕ · · · ⊕ xd = x ⊥

The masks (i ≥ 1): xi ← $ The masked variable: x0 ← x ⊕ x1 ⊕ · · · ⊕ xd

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-8
SLIDE 8

Higher-Order Masking

Basic principle

Every key-dependent variable x is shared into d + 1 variables

⊥ x0 ⊕ x1 ⊕ · · · ⊕ xd = x ⊥

The masks (i ≥ 1): xi ← $ The masked variable: x0 ← x ⊕ x1 ⊕ · · · ⊕ xd Note: equiv. d + 1 out of d + 1 secret sharing of x

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-9
SLIDE 9

Higher-Order Masking

Basic principle

Every key-dependent variable x is shared into d + 1 variables

⊥ x0 ⊕ x1 ⊕ · · · ⊕ xd = x ⊥

The masks (i ≥ 1): xi ← $ The masked variable: x0 ← x ⊕ x1 ⊕ · · · ⊕ xd Note: equiv. d + 1 out of d + 1 secret sharing of x Computation carried out by processing the shares separately

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-10
SLIDE 10

Higher-Order Masking

Soundness

[Chari-Jutla-Rao-Rohatgi CRYPTO’99]

Bit x masked → x0, x1, . . . , xd Leakage : Li ∼ xi + N(µ, σ2)

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-11
SLIDE 11

Higher-Order Masking

Soundness

[Chari-Jutla-Rao-Rohatgi CRYPTO’99]

Bit x masked → x0, x1, . . . , xd Leakage : Li ∼ xi + N(µ, σ2) Number of leakage samples to distinguish

  • (Li)i|x = 0
  • from
  • (Li)i|x = 1
  • :

q ≥ O(1)σd

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-12
SLIDE 12

Higher-Order Masking

Soundness

[Chari-Jutla-Rao-Rohatgi CRYPTO’99]

Bit x masked → x0, x1, . . . , xd Leakage : Li ∼ xi + N(µ, σ2) Number of leakage samples to distinguish

  • (Li)i|x = 0
  • from
  • (Li)i|x = 1
  • :

q ≥ O(1)σd Higher-order masking is sound in the presence of noisy leakage!

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-13
SLIDE 13

Higher-Order Masking Schemes

Definition A dth-order masking scheme for an encryption algorithm c ← E(m, k) is an algorithm (c0, c1, . . . , cd) ← E′ (m0, m1, . . . , md), (k0, k1, . . . , kd)

  • CHES 2010 – Provably Secure Higher-Order Masking of AES
slide-14
SLIDE 14

Higher-Order Masking Schemes

Definition A dth-order masking scheme for an encryption algorithm c ← E(m, k) is an algorithm (c0, c1, . . . , cd) ← E′ (m0, m1, . . . , md), (k0, k1, . . . , kd)

  • completeness:

i mi = m and i ki = k

  • ici = E(m, k)

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-15
SLIDE 15

Higher-Order Masking Schemes

Definition A dth-order masking scheme for an encryption algorithm c ← E(m, k) is an algorithm (c0, c1, . . . , cd) ← E′ (m0, m1, . . . , md), (k0, k1, . . . , kd)

  • completeness:

i mi = m and i ki = k

  • ici = E(m, k)

security: ∀(iv1, iv2, . . . , ivd) ∈ {intermediate var. of E′}d :

MI

  • (iv1, iv2, . . . , ivd), (m, k)
  • = 0

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-16
SLIDE 16

Higher-Order Masking Schemes

Definition A dth-order masking scheme for an encryption algorithm c ← E(m, k) is an algorithm (c0, c1, . . . , cd) ← E′ (m0, m1, . . . , md), (k0, k1, . . . , kd)

  • completeness:

i mi = m and i ki = k

  • ici = E(m, k)

security: ∀(iv1, iv2, . . . , ivd) ∈ {intermediate var. of E′}d :

MI

  • (iv1, iv2, . . . , ivd), (m, k)
  • = 0

For SPN (eg. DES, AES) the main issue is masking the S-box.

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-17
SLIDE 17

Higher-Order Masking Schemes

Literature

Software implementations:

[Schramm-Paar CT-RSA’06] ◮ secure only for d ≤ 2 [Coron-Prouff-Rivain CHES’07]

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-18
SLIDE 18

Higher-Order Masking Schemes

Literature

Software implementations:

[Schramm-Paar CT-RSA’06] ◮ secure only for d ≤ 2 [Coron-Prouff-Rivain CHES’07] [Rivain-Dottax-Prouff FSE’08] ◮ alternative solutions dedicated to d = 2

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-19
SLIDE 19

Higher-Order Masking Schemes

Literature

Software implementations:

[Schramm-Paar CT-RSA’06] ◮ secure only for d ≤ 2 [Coron-Prouff-Rivain CHES’07] [Rivain-Dottax-Prouff FSE’08] ◮ alternative solutions dedicated to d = 2

Hardware implementations:

[Ishai-Sahai-Wagner CRYPTO’03] ◮ every wire/logic gate is masked at an arbitrary order d ◮ wires values ≡ intermediate variables

⇒ dth-order masking scheme

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-20
SLIDE 20

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-21
SLIDE 21

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-22
SLIDE 22

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 a0b1 a0b2 a1b0 a1b1 a1b2 a2b0 a2b1 a2b2  

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-23
SLIDE 23

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 a0b1 a0b2 a1b1 a1b2 a2b2   ⊕   a1b0 a2b0 a2b1  

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-24
SLIDE 24

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 a0b1 a0b2 a1b1 a1b2 a2b2   ⊕   a1b0 a2b0 a2b1  

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-25
SLIDE 25

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 a0b1 ⊕ a1b0 a0b2 ⊕ a2b0 a1b1 a1b2 ⊕ a2b1 a2b2  

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-26
SLIDE 26

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 a0b1 ⊕ a1b0 a0b2 ⊕ a2b0 a1b1 a1b2 ⊕ a2b1 a2b2  

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-27
SLIDE 27

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 a0b1 ⊕ a1b0 a0b2 ⊕ a2b0 a1b1 a1b2 ⊕ a2b1 a2b2   ⊕   r1,2 r1,3 r2,3  

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-28
SLIDE 28

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 a0b1 ⊕ a1b0 a0b2 ⊕ a2b0 a1b1 a1b2 ⊕ a2b1 a2b2   ⊕   r1,2 r1,3 r1,2 r2,3 r1,3 r2,3  

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-29
SLIDE 29

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0 r1,2 a1b1 (a1b2 ⊕ r2,3) ⊕ a2b1 r1,3 r2,3 a2b2  

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-30
SLIDE 30

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0 r1,2 a1b1 (a1b2 ⊕ r2,3) ⊕ a2b1 r1,3 r2,3 a2b2  

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-31
SLIDE 31

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0 r1,2 a1b1 (a1b2 ⊕ r2,3) ⊕ a2b1 r1,3 r2,3 a2b2   c1 a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-32
SLIDE 32

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0 r1,2 a1b1 (a1b2 ⊕ r2,3) ⊕ a2b1 r1,3 r2,3 a2b2   c1 c2 a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-33
SLIDE 33

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0 r1,2 a1b1 (a1b2 ⊕ r2,3) ⊕ a2b1 r1,3 r2,3 a2b2   c1 c2 c3 a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-34
SLIDE 34

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0 r1,2 a1b1 (a1b2 ⊕ r2,3) ⊕ a2b1 r1,3 r2,3 a2b2   c1 c2 c3 a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-35
SLIDE 35

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0 r1,2 a1b1 (a1b2 ⊕ r2,3) ⊕ a2b1 r1,3 r2,3 a2b2   c1 c2 c3 a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0

Ishai et al. prove (d/2)th-order security

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-36
SLIDE 36

Ishai-Sahai-Wagner (ISW) Scheme

Principle

AND gates encoding: ◮ Input: (ai)i, (bi)i s.t.

i ai = a, i bi = b

◮ Output: (ci)i s.t.

i ci = ab

  • ici =
  • iai
  • ibi
  • =
  • i,jaibj

Example (d = 2):

  a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0 r1,2 a1b1 (a1b2 ⊕ r2,3) ⊕ a2b1 r1,3 r2,3 a2b2   c1 c2 c3 a0b0 (a0b1 ⊕ r1,2) ⊕ a1b0 (a0b2 ⊕ r1,3) ⊕ a2b0

Ishai et al. prove (d/2)th-order security ◮ We prove dth-order security

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-37
SLIDE 37

Ishai-Sahai-Wagner (ISW) Scheme

Example: AND gate for d = 2

b b b b b b b b b b b b b b b b b b b b b

(ai)i c0 c1 c2 (bi)i $ $ $

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-38
SLIDE 38

Ishai-Sahai-Wagner (ISW) Scheme

Practical Issues

Important area overhead for the masked circuit ◮ A wire is encoded by d + 1 wires ◮ One AND gate encoded by

(d + 1)2 ANDs + 2d(d + 1) XORs + d(d + 1)/2 $

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-39
SLIDE 39

Ishai-Sahai-Wagner (ISW) Scheme

Practical Issues

Important area overhead for the masked circuit ◮ A wire is encoded by d + 1 wires ◮ One AND gate encoded by

(d + 1)2 ANDs + 2d(d + 1) XORs + d(d + 1)/2 $

◮ Example: AES S-box circuit

ISW No masking d = 1 d = 2 d = 3 200 gates 500 gates 1.1 Kgates 2 Kgates

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-40
SLIDE 40

Ishai-Sahai-Wagner (ISW) Scheme

Practical Issues

Important area overhead for the masked circuit ◮ A wire is encoded by d + 1 wires ◮ One AND gate encoded by

(d + 1)2 ANDs + 2d(d + 1) XORs + d(d + 1)/2 $

◮ Example: AES S-box circuit

ISW No masking d = 1 d = 2 d = 3 200 gates 500 gates 1.1 Kgates 2 Kgates

Practical security issue with glitches ◮ addition of synchronizing elements ⇒ additional overhead

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-41
SLIDE 41

Ishai-Sahai-Wagner (ISW) Scheme

Practical Issues

Important area overhead for the masked circuit ◮ A wire is encoded by d + 1 wires ◮ One AND gate encoded by

(d + 1)2 ANDs + 2d(d + 1) XORs + d(d + 1)/2 $

◮ Example: AES S-box circuit

ISW No masking d = 1 d = 2 d = 3 200 gates 500 gates 1.1 Kgates 2 Kgates

Practical security issue with glitches ◮ addition of synchronizing elements ⇒ additional overhead Not suitable for software implementations

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-42
SLIDE 42

Outline 1 Introduction

Higher-Order Masking ISW Scheme (CRYPTO’03)

2 Our Scheme

Masking the S-box Masking the Whole AES Security Implementation Results

3 Conclusion

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-43
SLIDE 43

Masking the S-box

Non-linearity ⇒ difficulty to mask

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-44
SLIDE 44

Masking the S-box

Non-linearity ⇒ difficulty to mask We use the AES S-box structure: S = Exp ◦ Af ◮ Af: affine transformation over F8

2

◮ Exp : x → x254 over F256

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-45
SLIDE 45

Masking the S-box

Non-linearity ⇒ difficulty to mask We use the AES S-box structure: S = Exp ◦ Af ◮ Af: affine transformation over F8

2

◮ Exp : x → x254 over F256 Masking Af is easy:

Af(x) = Af(x0) ⊕ Af(x1) ⊕ · · · ⊕ Af(xd) ⊕ 0x63 iff d is odd

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-46
SLIDE 46

Masking the S-box

Non-linearity ⇒ difficulty to mask We use the AES S-box structure: S = Exp ◦ Af ◮ Af: affine transformation over F8

2

◮ Exp : x → x254 over F256 Masking Af is easy:

Af(x) = Af(x0) ⊕ Af(x1) ⊕ · · · ⊕ Af(xd) ⊕ 0x63 iff d is odd

For Exp we use an exponentiation algorithm ◮ approach used for 1st-order masking in

[Bl¨

  • mer-Merchan-Krummel SAC’04]

◮ we want to design a dth-order secure exponentiation ◮ we need dth-order secure square and multiplication

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-47
SLIDE 47

Masking the S-box

dth-order secure square ◮ squaring is linear over F256

x2

0 ⊕ x2 1 ⊕ · · · ⊕ x2 d = x2

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-48
SLIDE 48

Masking the S-box

dth-order secure square ◮ squaring is linear over F256

x2j

0 ⊕ x2j 1 ⊕ · · · ⊕ x2j d = x2j

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-49
SLIDE 49

Masking the S-box

dth-order secure square ◮ squaring is linear over F256

x2j

0 ⊕ x2j 1 ⊕ · · · ⊕ x2j d = x2j

dth-order secure multiplication ◮ we generalize the ISW scheme to F256

AND ⇒ F256 multiplication XOR ⇒ F256 addition (8-bit XOR) $1 ⇒ $8 (random 8-bit value)

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-50
SLIDE 50

Masking the S-box

dth-order secure square ◮ squaring is linear over F256

x2j

0 ⊕ x2j 1 ⊕ · · · ⊕ x2j d = x2j

dth-order secure multiplication ◮ we generalize the ISW scheme to F256

AND ⇒ F256 multiplication XOR ⇒ F256 addition (8-bit XOR) $1 ⇒ $8 (random 8-bit value)

Complexity: ◮ secure square: d + 1 squares ◮ secure mult: (d + 1)2 mult, 2d(d + 1) XOR, d(d + 1)/2 $8

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-51
SLIDE 51

Masking the S-box

dth-order secure square ◮ squaring is linear over F256

x2j

0 ⊕ x2j 1 ⊕ · · · ⊕ x2j d = x2j

dth-order secure multiplication ◮ we generalize the ISW scheme to F256

AND ⇒ F256 multiplication XOR ⇒ F256 addition (8-bit XOR) $1 ⇒ $8 (random 8-bit value)

Complexity: ◮ secure square: d + 1 squares ◮ secure mult: (d + 1)2 mult, 2d(d + 1) XOR, d(d + 1)/2 $8 Our goal: minimize the number of multiplications which are

not squares

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-52
SLIDE 52

Masking the S-box

The proposed addition chain:

x

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-53
SLIDE 53

Masking the S-box

The proposed addition chain:

x x2

2

  • ne square

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-54
SLIDE 54

Masking the S-box

The proposed addition chain:

x x2 x3

2

  • ne square
  • ne mult

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-55
SLIDE 55

Masking the S-box

The proposed addition chain:

x x2 x3 x12

2 4

  • ne square
  • ne mult
  • neˆ4 (two squares)

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-56
SLIDE 56

Masking the S-box

The proposed addition chain:

x x2 x3 x12 x15

2 4

  • ne square
  • ne mult
  • neˆ4 (two squares)
  • ne mult

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-57
SLIDE 57

Masking the S-box

The proposed addition chain:

x x2 x3 x12 x240 x15

2 16 4

  • ne square
  • ne mult
  • neˆ4 (two squares)
  • ne mult
  • neˆ16 (four squares)

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-58
SLIDE 58

Masking the S-box

The proposed addition chain:

x x2 x3 x12 x240 x15 x252

2 16 4

  • ne square
  • ne mult
  • neˆ4 (two squares)
  • ne mult
  • neˆ16 (four squares)
  • ne mult

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-59
SLIDE 59

Masking the S-box

The proposed addition chain:

x x2 x3 x12 x240 x15 x252 x254

2 16 4

  • ne square
  • ne mult
  • neˆ4 (two squares)
  • ne mult
  • neˆ16 (four squares)
  • ne mult
  • ne mult

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-60
SLIDE 60

Masking the S-box

The proposed addition chain:

x x2 x3 x12 x240 x15 x252 x254

2 16 4

  • ne square
  • ne mult
  • neˆ4 (two squares)
  • ne mult
  • neˆ16 (four squares)
  • ne mult
  • ne mult

Total: 4 mult and 7

squares

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-61
SLIDE 61

Masking the S-box

The proposed addition chain:

x x2 x3 x12 x240 x15 x252 x254

2 16 4

  • ne square
  • ne mult
  • neˆ4 (two squares)
  • ne mult
  • neˆ16 (four squares)
  • ne mult
  • ne mult

Total: 4 mult and 7

squares

Memory: 3 registers

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-62
SLIDE 62

Masking the S-box

The proposed addition chain:

x x2 x3 x12 x240 x15 x252 x254

2 16 4

  • ne square
  • ne mult
  • neˆ4 (two squares)
  • ne mult
  • neˆ16 (four squares)
  • ne mult
  • ne mult

Total: 4 mult and 7

squares

Memory: 3 registers LUT forˆ2,ˆ4 andˆ16

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-63
SLIDE 63

Masking the S-box

Algorithmic description: Input: shares xi s.t.

i xi = x

Output: shares yi s.t.

i yi = x254

  • 1. (zi)i ← (x2

i )i

[

i zi = x2]

  • 2. RefreshMasks
  • (zi)i
  • 3. (yi)i ← SecMult
  • (zi)i, (xi)i
  • [

i yi = x3]

  • 4. (wi)i ← (y4

i )i

[

i wi = x12]

  • 5. RefreshMasks
  • (wi)i
  • 6. (yi)i ← SecMult
  • (yi)i, (wi)i
  • [

i yi = x15]

  • 7. (yi)i ← (y16

i )i

[

i yi = x240]

  • 8. (yi)i ← SecMult
  • (yi)i, (wi)i
  • [

i yi = x252]

  • 9. (yi)i ← SecMult
  • (yi)i, (zi)i
  • [

i yi = x254]

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-64
SLIDE 64

Masking the S-box

Algorithmic description: Input: shares xi s.t.

i xi = x

Output: shares yi s.t.

i yi = x254

  • 1. (zi)i ← (x2

i )i

[

i zi = x2]

  • 2. RefreshMasks
  • (zi)i
  • 3. (yi)i ← SecMult
  • (zi)i, (xi)i
  • [

i yi = x3]

  • 4. (wi)i ← (y4

i )i

[

i wi = x12]

  • 5. RefreshMasks
  • (wi)i
  • 6. (yi)i ← SecMult
  • (yi)i, (wi)i
  • [

i yi = x15]

  • 7. (yi)i ← (y16

i )i

[

i yi = x240]

  • 8. (yi)i ← SecMult
  • (yi)i, (wi)i
  • [

i yi = x252]

  • 9. (yi)i ← SecMult
  • (yi)i, (zi)i
  • [

i yi = x254]

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-65
SLIDE 65

Masking the S-box

Algorithmic description: Input: shares xi s.t.

i xi = x

Output: shares yi s.t.

i yi = x254

  • 1. (zi)i ← (x2

i )i

[

i zi = x2]

  • 2. RefreshMasks
  • (zi)i
  • 3. (yi)i ← SecMult
  • (zi)i, (xi)i
  • [

i yi = x3]

  • 4. (wi)i ← (y4

i )i

[

i wi = x12]

  • 5. RefreshMasks
  • (wi)i
  • 6. (yi)i ← SecMult
  • (yi)i, (wi)i
  • [

i yi = x15]

  • 7. (yi)i ← (y16

i )i

[

i yi = x240]

  • 8. (yi)i ← SecMult
  • (yi)i, (wi)i
  • [

i yi = x252]

  • 9. (yi)i ← SecMult
  • (yi)i, (zi)i
  • [

i yi = x254]

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-66
SLIDE 66

Masking the S-box

Algorithmic description: Input: shares xi s.t.

i xi = x

Output: shares yi s.t.

i yi = x254

  • 1. (zi)i ← (x2

i )i

[

i zi = x2]

  • 2. RefreshMasks
  • (zi)i
  • 3. (yi)i ← SecMult
  • (zi)i, (xi)i
  • [

i yi = x3]

  • 4. (wi)i ← (y4

i )i

[

i wi = x12]

  • 5. RefreshMasks
  • (wi)i
  • 6. (yi)i ← SecMult
  • (yi)i, (wi)i
  • [

i yi = x15]

  • 7. (yi)i ← (y16

i )i

[

i yi = x240]

  • 8. (yi)i ← SecMult
  • (yi)i, (wi)i
  • [

i yi = x252]

  • 9. (yi)i ← SecMult
  • (yi)i, (zi)i
  • [

i yi = x254]

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-67
SLIDE 67

Masking the Whole AES

Linear operations of encryption/key schedule (ShiftRows,

MixColumns, RotWord) processed on every share independently Λ

  • ixi
  • =
  • iΛ(xi)

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-68
SLIDE 68

Masking the Whole AES

Linear operations of encryption/key schedule (ShiftRows,

MixColumns, RotWord) processed on every share independently Λ

  • ixi
  • =
  • iΛ(xi)

Key addition performed by adding each key-share to one

single state-share

  • isi
  • iki
  • =
  • i(si ⊕ ki)

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-69
SLIDE 69

Security

dth-order security ∀(iv1, iv2, . . . , ivd) ∈ {intermediate var. of E′}d : MI

  • (iv1, iv2, . . . , ivd), (m, k)
  • = 0

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-70
SLIDE 70

Security

dth-order security ∀(iv1, iv2, . . . , ivd) ∈ {intermediate var. of E′}d : MI

  • (iv1, iv2, . . . , ivd), (m, k)
  • = 0

Algorithm split into several transformations applied to

  • ne/two dth-order masked value(s)

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-71
SLIDE 71

Security

dth-order security ∀(iv1, iv2, . . . , ivd) ∈ {intermediate var. of E′}d : MI

  • (iv1, iv2, . . . , ivd), (m, k)
  • = 0

Algorithm split into several transformations applied to

  • ne/two dth-order masked value(s)

Every transformation is locally secure ◮ all transformations are linear (straightforward security) except

the field multiplication

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-72
SLIDE 72

Security

dth-order security ∀(iv1, iv2, . . . , ivd) ∈ {intermediate var. of E′}d : MI

  • (iv1, iv2, . . . , ivd), (m, k)
  • = 0

Algorithm split into several transformations applied to

  • ne/two dth-order masked value(s)

Every transformation is locally secure ◮ all transformations are linear (straightforward security) except

the field multiplication

◮ field multiplication secured using ISW scheme ◮ improved security proof for ISW scheme

d/2 → d

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-73
SLIDE 73

Security

dth-order security ∀(iv1, iv2, . . . , ivd) ∈ {intermediate var. of E′}d : MI

  • (iv1, iv2, . . . , ivd), (m, k)
  • = 0

Algorithm split into several transformations applied to

  • ne/two dth-order masked value(s)

Every transformation is locally secure ◮ all transformations are linear (straightforward security) except

the field multiplication

◮ field multiplication secured using ISW scheme ◮ improved security proof for ISW scheme

d/2 → d

Local security for every transformation implies global security

for the whole algorithm

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-74
SLIDE 74

Implementation Results (8051)

Method K cycles ms (31MHz) RAM (bytes) ROM (bytes) Unprotected Implementation Na. 3 0.1 32 1150 First-Order Masking [Messerges FSE’00] 10 0.3 256+35 1553 [Oswald+ FSE’05] 77 2.5 42 3195 Our scheme (d=1) 129 4 73 3153 Second-Order Masking [Schramm+ CT-RSA’06] 594 19 512+90 2336 [Rivain+ FSE’08] 672 22 256+86 2215 Our scheme (d=2) 271 9 79 3845 Third-Order Masking Our scheme (d=3) 470 15 103 4648

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-75
SLIDE 75

Implementation Results (8051)

Method K cycles ms (31MHz) RAM (bytes) ROM (bytes) Unprotected Implementation Na. 3 0.1 32 1150 First-Order Masking [Messerges FSE’00] 10 0.3 256+35 1553 [Oswald+ FSE’05] 77 2.5 42 3195 Our scheme (d=1) 129 4 73 3153 Second-Order Masking [Schramm+ CT-RSA’06] 594 19 512+90 2336 [Rivain+ FSE’08] 672 22 256+86 2215 Our scheme (d=2) 271 9 79 3845 Third-Order Masking Our scheme (d=3) 470 15 103 4648

Interpolation: 30d2 + 50d + 50 K cycles ◮ d = 4 : 730 Kc / 24 ms ◮ d = 5 : 1050 Kc / 34 ms

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-76
SLIDE 76

Outline 1 Introduction

Higher-Order Masking ISW Scheme (CRYPTO’03)

2 Our Scheme

Masking the S-box Masking the Whole AES Security Implementation Results

3 Conclusion

CHES 2010 – Provably Secure Higher-Order Masking of AES

slide-77
SLIDE 77

Conclusion

First masking scheme for software implementations of AES

with provable security at any order

Based on the work [Ishai-Sahai-Wagner CRYPTO’03] Generalization: secure field multiplication in software Improved security proof (d/2 → d), significant in practice On-going work: ◮ generalization to any S-box/SPN ◮ formal security model for dth-order secure implementations

CHES 2010 – Provably Secure Higher-Order Masking of AES